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MPC857T PowerQUICC™

User's Manual

MPC857TUM/D

Rev. 0, 11/2000

™

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Page 1 MPC857T PowerQUICC™ User’s Manual MPC857TUM/D Rev. 0, 11/2000 ™...
Page 2 DigitalDNA, Mfax, PowerQUICC, and PowerQUICC II are trademarks of Motorola, Inc. The PowerPC name, the PowerPC logotype, and PowerPC 603e are trademarks of International Business Machines Corporation used by Motorola under license from International Business Machines Corporation. C is a registered trademark of Philips Semiconductors Information in this document is provided solely to enable system and software implementers to use PowerPC microprocessors.
Page 3 Part I—Overview MPC857T Overview Memory Map Part II—PowerPC Microprocessor Module PowerPC Core PowerPC Core Register Set MPC857T Instruction Set Exceptions Instruction and Data Caches Memory Management Unit Instruction Execution Timing Part III—PowerPC Microprocessor Module System Interface Unit Reset Part IV—Hardware Interface External Signals External Bus Interface Clocks and Power Control...
Page 4 Part I—Overview MPC857T Overview Memory Map Part II—PowerPC Microprocessor Module PowerPC Core PowerPC Core Register Set MPC857T Instruction Set Exceptions Instruction and Data Caches Memory Management Unit Instruction Execution Timing Part III—PowerPC Microprocessor Module System Interface Unit Reset Part IV—Hardware Interface External Signals External Bus Interface Clocks and Power Control...
Page 5 Part V—Communications Processor Module Communications Processor Module and Timers Communications Processor SDMA Channels and IDMA Emulation Serial Interface SCC Introduction SCC UART Mode SCC HDLC Mode SCC AppleTalk Mode SCC Asynchronous HDLC Mode and IrDA SCC BISYNC Mode SCC Ethernet Mode SCC Transparent Mode Serial Management Controllers Serial Peripheral Interface...
Page 6 Part V—Communications Processor Module Communications Processor Module and Timers Communications Processor SDMA Channels and IDMA Emulation Serial Interface SCC Introduction SCC UART Mode SCC HDLC Mode SCC AppleTalk Mode SCC Asynchronous HDLC Mode and IrDA SCC BISYNC Mode SCC Ethernet Mode SCC Transparent Mode Serial Management Controllers Serial Peripheral Interface...
Page 7: Table Of Contents
CONTENTS Paragraph Page Title Number Number Part I Overview Chapter 1 MPC857T Overview Features ....................... 1-2 Embedded PowerPC Core................... 1-7 System Interface Unit (SIU) ................1-8 PCMCIA Controller.................... 1-8 Power Management .................... 1-8 Communications Processor Module (CPM) ............1-9 ATM Capabilities....................1-10 Software Compatibility Issues ................
Page 8 CONTENTS Paragraph Page Title Number Number Register Set ....................... 3-10 Execution Units....................3-10 3.6.1 Branch Processing Unit ................3-11 3.6.2 Integer Unit ....................3-11 3.6.3 Load/Store Unit..................... 3-11 3.6.3.1 Executing Load/Store Instructions ............3-13 3.6.3.2 Serializing Load/Store Instructions ............3-13 3.6.3.3 Store Accesses ..................
Page 9 CONTENTS Paragraph Page Title Number Number 5.2.1.2 Defined Instruction Class ................5-4 5.2.1.3 Illegal Instruction Class ................5-4 5.2.1.4 Reserved Instruction Class ................. 5-5 5.2.2 Addressing Modes ..................5-5 5.2.2.1 Memory Addressing ................... 5-5 5.2.2.2 Effective Address Calculation ..............5-6 5.2.2.3 Synchronization ..................
Page 10 CONTENTS Paragraph Page Title Number Number Chapter 6 Exceptions Exceptions......................6-2 6.1.1 Exception Ordering..................6-3 6.1.2 PowerPC-Defined Exceptions ................ 6-4 6.1.2.1 System Reset Interrupt (0x00100) .............. 6-4 6.1.2.2 Machine Check Interrupt (0x00200) ............6-5 6.1.2.3 DSI Exception (0x00300) ................6-6 6.1.2.4 ISI Exception (0x00400)................
Page 11 CONTENTS Paragraph Page Title Number Number 7.3.1.2.4 Instruction Cache Unlock All Command ..........7-13 7.3.1.2.5 Instruction Cache Invalidate All Command ......... 7-13 7.3.2 Data Cache Control Registers............... 7-13 7.3.2.1 Reading Data Cache Tags and Copyback Buffer ........7-16 7.3.2.2 DC_CST Commands ................7-17 7.3.2.2.1 Data Cache Enable/Disable Commands ..........
Page 12 CONTENTS Paragraph Page Title Number Number Memory Management Unit Features ....................... 8-1 PowerPC Architecture Compliance ..............8-2 Address Translation .................... 8-3 8.3.1 Translation Disabled ..................8-3 8.3.2 Translation Enabled ..................8-3 8.3.3 TLB Operation....................8-5 Using Access Protection Groups ................ 8-6 Protection Resolution Modes................
Page 13 CONTENTS Paragraph Page Title Number Number Chapter 9 Instruction Execution Timing Instruction Execution Timing Examples ............9-1 9.1.1 Data Cache Load with a Data Dependency ............ 9-1 9.1.2 Writeback Arbitration ..................9-2 9.1.3 Private Writeback Bus Load ................9-3 9.1.4 Fastest External Load (Data Cache Miss)............
Page 14 CONTENTS Paragraph Page Title Number Number 10.7 The Software Watchdog Timer............... 10-21 10.7.1 Software Service Register (SWSR) ............10-22 10.8 The PowerPC Decrementer................10-23 10.8.1 Decrementer Register (DEC)..............10-24 10.9 The PowerPC Timebase.................. 10-24 10.9.1 Timebase Register (TBU and TBL)............10-25 10.9.2 Timebase Reference Registers (TBREFA and TBREFB)......
Page 15 CONTENTS Paragraph Page Title Number Number Part IV The Hardware Interface Chapter 12 External Signals 12.1 System Bus Signals................... 12-5 12.2 Active Pull-Up Buffers ................... 12-23 12.3 Internal Pull-Up and Pull-Down Resistors ............ 12-25 12.4 Recommended Basic Pin Connections ............12-25 12.4.1 Reset Configuration ..................
Page 16 CONTENTS Paragraph Page Title Number Number 13.4.7.3.3 Transfer Size (TSIZ)................13-32 13.4.7.3.4 Address Types (AT) ................13-32 13.4.7.3.5 Burst Data in Progress (BDIP) ............13-35 13.4.8 Termination Signals..................13-35 13.4.8.1 Transfer Acknowledge (TA)..............13-35 13.4.8.2 Burst Inhibit (BI) ..................13-35 13.4.8.3 Transfer Error Acknowledge (TEA)............
Page 17 CONTENTS Paragraph Page Title Number Number 14.4.3 Clock Synthesizer Power (VDDSYN, VSSSYN, VSSYN1) ..... 14-18 14.4.4 Keep-Alive Power (KAPWR) ..............14-18 14.5 Power Control (Low-Power Modes)............... 14-18 14.5.1 Normal High Mode..................14-21 14.5.2 Normal Low Mode..................14-21 14.5.3 Doze High Mode..................14-21 14.5.4 Doze Low Mode ..................
Page 18 CONTENTS Paragraph Page Title Number Number 15.4.7 Memory Address Register (MAR) ............. 15-17 15.4.8 Memory Periodic Timer Prescaler Register (MPTPR)....... 15-18 15.5 General-Purpose Chip-Select Machine (GPCM)..........15-18 15.5.1 Timing Configuration ................. 15-19 15.5.1.1 Chip-Select Assertion Timing ..............15-20 15.5.1.2 Chip-Select and Write Enable Deassertion Timing........ 15-21 15.5.1.3 Relaxed Timing ..................
Page 19 CONTENTS Paragraph Page Title Number Number 15.8.4.1 Address Incrementing for External Synchronous Bursting Masters ..15-55 15.8.4.2 Handshake Mechanism for Asynchronous External Masters ....15-56 15.8.4.3 Special Signal for External Address Multiplexer Control ...... 15-56 15.8.5 External Master Examples ................15-56 15.8.5.1 External Masters and the GPCM ............
Page 20 CONTENTS Paragraph Page Title Number Number Chapter 17 Communications Processor Module and CPM Timers 17.1 Features ......................17-2 17.2 CPM General-Purpose Timers................17-4 17.2.1 Features......................17-5 17.2.2 CPM Timer Operation .................. 17-6 17.2.2.1 Timer Clock Source .................. 17-6 17.2.2.2 Timer Reference Count................17-6 17.2.2.3 Timer Capture ...................
Page 21 CONTENTS Paragraph Page Title Number Number 18.7.2 The set timer Command................18-13 18.7.3 RISC Timer Table Parameter RAM and Timer Table Entries ....18-13 18.7.3.1 RISC Timer Command Register (TM_CMD)........18-15 18.7.3.2 RISC Timer Table Entries ..............18-15 18.7.4 RISC Timer Event Register (RTER)/Mask Register (RTMR)....18-15 18.7.5 PWM Mode....................
Page 22 CONTENTS Paragraph Page Title Number Number 19.3.8.2 Single-Address (Single-Cycle) Transfer (Fly-By)........19-16 19.3.9 Single-Buffer Mode on IDMA1ÑA Special Case ........19-18 19.3.9.1 IDMA1 Channel Mode Register (DCMR) (Single-Buffer Mode) ..19-19 19.3.9.2 IDMA1 Status Register (IDSR1) (Single-Buffer Mode)......19-19 19.3.9.3 IDMA1 Mask Register (IDMR1) (Single-Buffer Mode) .......
Page 23 CONTENTS Paragraph Page Title Number Number 21.2.3 Data Synchronization Register (DSR)............21-9 21.2.4 Transmit-on-Demand Register (TODR)............21-9 21.3 SCC Buffer Descriptors (BDs) ............... 21-10 21.4 SCC Parameter RAM..................21-12 21.4.1 Function Code Registers (RFCR and TFCR) ..........21-14 21.4.2 Handling SCC Interrupts ................21-14 21.4.3 SCC Initialization ..................
Page 24 CONTENTS Paragraph Page Title Number Number 22.19 SCC UART Event Register (SCCE) and Mask Register (SCCM) ....22-19 22.20 SCC UART Status Register (SCCS) .............. 22-21 22.21 SCC UART Programming Example............... 22-22 22.22 S-Records Loader Application................ 22-23 Chapter 23 SCC HDLC Mode 23.1 SCC HDLC Features..................
Page 25 CONTENTS Paragraph Page Title Number Number 24.4.3 Programming the TODR................24-4 24.4.4 SCC AppleTalk Programming Example............24-4 Chapter 25 SCC Asynchronous HDLC Mode and IrDA 25.1 Asynchronous HDLC Features ................. 25-1 25.2 Asynchronous HDLC Frame Transmission Processing ........25-2 25.3 Asynchronous HDLC Frame Reception Processing.........
Page 26 CONTENTS Paragraph Page Title Number Number 26.10 Handling Errors in the SCC BISYNC .............. 26-9 26.11 BISYNC Mode Register (PSMR)..............26-10 26.12 SCC BISYNC Receive BD (RxBD)............... 26-12 26.13 SCC BISYNC Transmit BD (TxBD).............. 26-13 26.14 BISYNC Event Register (SCCE)/BISYNC Mask Register (SCCM)..... 26-15 26.15 SCC Status Registers (SCCS).................
Page 27 CONTENTS Paragraph Page Title Number Number Chapter 28 SCC Transparent Mode 28.1 Features ......................28-1 28.2 SCC Transparent Channel Frame Transmission Process........28-2 28.3 SCC Transparent Channel Frame Reception Process........28-2 28.4 Achieving Synchronization in Transparent Mode ..........28-3 28.4.1 Synchronization in NMSI Mode..............
Page 28 CONTENTS Paragraph Page Title Number Number 29.2.5 Saving Power ....................29-9 29.2.6 Handling Interrupts In the SMC ..............29-9 29.3 SMC in UART Mode..................29-9 29.3.1 SMC UART Features.................. 29-10 29.3.2 SMC UART-Specific Parameter RAM ............29-10 29.3.3 SMC UART Channel Transmission Process ..........29-11 29.3.4 SMC UART Channel Reception Process ...........
Page 29 CONTENTS Paragraph Page Title Number Number 29.5.9 SMC GCI Event Register (SMCE)/Mask Register (SMCM)..... 29-36 Chapter 30 Serial Peripheral Interface (SPI) 30.1 Features ......................30-2 30.2 SPI Clocking and Signal Functions ..............30-2 30.3 Configuring the SPI Controller................. 30-3 30.3.1 The SPI as a Master Device................
Page 30 CONTENTS Paragraph Page Title Number Number 31.4.4 C Event/Mask Registers (I2CER/I2CMR) ..........31-8 31.4.5 C Command Register (I2COM)..............31-8 31.5 I2C Parameter RAM ..................31-9 31.6 I2C Commands ....................31-11 31.7 I2C Buffer Descriptor (BD) Tables ..............31-11 31.7.1 C Buffer Descriptors (BDs) ..............31-12 31.7.1.1 C Receive Buffer Descriptor (RxBD)..........
Page 31 CONTENTS Paragraph Page Title Number Number Chapter 33 Parallel I/O Ports 33.1 Features ......................33-2 33.2 Port A ........................ 33-2 33.2.1 Port A Registers .................... 33-3 33.2.1.1 Port A Open-Drain Register (PAODR) ............ 33-3 33.2.1.2 Port A Data Register (PADAT) ..............33-4 33.2.1.3 Port A Data Direction Register (PADIR) ..........
Page 32 CONTENTS Paragraph Page Title Number Number CPM Interrupt Controller 34.1 Features ......................34-1 34.2 CPM Interrupt Source Priorities ............... 34-2 34.2.1 Highest Priority Interrupt................34-3 34.2.2 Nested Interrupts................... 34-3 34.3 Masking Interrupt Sources in the CPM ............34-4 34.4 Generating and Calculating Interrupt Vectors ..........34-5 34.5 CPIC Registers....................
Page 33 CONTENTS Paragraph Page Title Number Number 35.9 ATM Pace Control (APC) ................35-12 35.10 Internal and External Channels (Extended Channel Mode) ......35-12 35.11 ATM Port-to-Port (PTP) Cell Switching ............35-13 35.12 Memory-to-Memory SAR ................35-13 35.13 General ATM Initialization Requirement............35-14 Chapter 36 Buffer Descriptors and Connection Tables 36.1...
Page 34 CONTENTS Paragraph Page Title Number Number 38.1.2.3 Address Compression Example ..............38-4 38.1.2.4 Preventing Channel Aliasing ..............38-4 38.1.2.5 OAM Screening ..................38-5 38.1.3 CAM Address Mapping (SRSTATE[EXT,ACP] = 10) ....... 38-5 38.2 Port-to-Port (PTP) Switching................38-5 38.2.1 PTP Switching Mechanism................38-5 38.2.2 PTP Buffers....................
Page 35 CONTENTS Paragraph Page Title Number Number Chapter 41 Interface Configuration 41.1 General ATM Registers ..................41-1 41.1.1 Port D Pin Assignment Register (PDPAR)........... 41-1 41.1.2 APC Timer (CPM Timer 4) ................41-2 41.1.3 RISC Timer....................41-2 41.2 UTOPIA Mode Registers.................. 41-2 41.2.1 System Clock Control Register (SCCR)............
Page 36 CONTENTS Paragraph Page Title Number Number 43.2.1 Transceiver Connection ................43-3 43.2.2 FEC Frame Transmission ................43-4 43.2.3 FEC Frame Reception................... 43-4 43.2.4 CAM Interface ....................43-6 43.2.5 FEC Command Set ..................43-6 43.2.6 Ethernet Address Recognition ..............43-6 43.2.7 Hash Table Algorithm ..................
Page 37 CONTENTS Paragraph Page Title Number Number 43.4.2.2 User Initialization (before Setting ECNTRL[ETHER_EN])....43-34 43.4.2.2.1 Descriptor Controller Initialization ............ 43-35 43.4.2.2.2 User Initialization (after Setting ECNTRL[ETHER_EN])....43-35 43.4.3 Buffer Descriptors (BDs)................43-35 43.4.3.1 Ethernet Receive Buffer Descriptor (RxBD).......... 43-36 43.4.3.2 Ethernet Transmit Buffer Descriptor (TxBD) ........43-37 Part VIII System Debugging and Testing Support Chapter 44...
Page 38 CONTENTS Paragraph Page Title Number Number 44.2.4.4 Ignore First Match .................. 44-17 44.2.4.5 Generating Six Compare Types.............. 44-18 44.2.5 Load/Store Breakpoint Example..............44-18 44.3 Development System Interface ............... 44-19 44.3.1 Debug Mode Operation ................44-21 44.3.1.1 Debug Mode Enable vs. Debug Mode Disable ........44-22 44.3.1.2 Entering Debug Mode................
Page 39 CONTENTS Paragraph Page Title Number Number 44.5.1.7 (COUNTA/COUNTB) ................44-43 44.5.2 Debug Mode Registers................44-44 44.5.2.1 Interrupt Cause Register (ICR) ............... 44-44 44.5.2.2 Debug Enable Register (DER)..............44-45 44.5.2.3 Development Port Data Register (DPDR) ..........44-47 Chapter 45 IEEE 1149.1 Test Access Port 45.1 Overview......................
Page 40 CONTENTS Paragraph Page Title Number Number B.3.3 Performance Calculations ................B-5 ATM Performance ....................B-8 Receiver ......................B-8 Transmitter......................B-10 Appendix C Register Quick Reference Guide PowerPC RegistersÑUser Registers ..............C-1 PowerPC RegistersÑSupervisor Registers ............C-2 MPC857T-Specific SPRs ................... C-3 Appendix D Instruction Set Listings Instructions Sorted by Mnemonic..............
Page 41 ILLUSTRATIONS Figure Page Title Number Number MPC857T Block Diagram .................... 1-6 Block Diagram of the Core ................... 3-5 Instruction Flow Conceptual Diagram................3-7 Basic Instruction Pipeline Timing ................3-8 Sequencer Data Path ..................... 3-9 LSU Functional Block Diagram ................. 3-12 Condition Register (CR) ....................
Page 42 ILLUSTRATIONS Figure Page Title Number Number 8-18 IMMU RAM Entry Read Register 0 (MI_RAM0) ............. 8-26 8-19 IMMU RAM Entry Read Register 1 (MI_RAM1) ............. 8-27 8-20 DMMU CAM Entry Read Register (MD_CAM)............8-28 8-21 DMMU RAM Entry Read Register 0 (MD_RAM0)..........8-29 8-22 DMMU RAM Entry Read Register 1 (MD_RAM1)..........
Page 43 ILLUSTRATIONS Figure Page Title Number Number 10-27 Real-Time Clock Alarm Seconds Register (RTSEC)..........10-30 10-28 Periodic Interrupt Timer Block Diagram..............10-31 10-29 Periodic Interrupt Status and Control Register (PISCR) .......... 10-32 10-30 PIT Count Register (PITC) ..................10-33 10-31 PIT Register (PITR)....................10-34 11-1 Power-On and Hard Reset Sequence ................
Page 44 ILLUSTRATIONS Figure Page Title Number Number 13-28 Reservation on Multilevel Bus Hierarchy..............13-39 13-29 Retry Transfer TimingÐInternal Arbiter ..............13-41 13-30 Retry Transfer TimingÐExternal Arbiter ..............13-42 13-31 Retry on Burst Cycle....................13-43 14-1 Clock Source and Distribution..................14-2 14-2 Clock Module Components ..................
Page 45 ILLUSTRATIONS Figure Page Title Number Number 15-21 GPCM Relaxed Timing Read (ACS = 1x, SCY = 1, CSNT = 0, and TRLX = 1) ........................ 15-23 15-22 GPCM Relaxed-Timing Write (ACS = 1x, SCY = 0, CSNT = 0, TRLX = 1) ..15-24 15-23 GPCM Relaxed-Timing Write (ACS = 1x, SCY = 0, CSNT = 1, TRLX =1) ..
Page 46 ILLUSTRATIONS Figure Page Title Number Number 15-61 Exception Cycle ......................15-72 15-62 Optimized DRAM Burst Read Access ..............15-73 15-63 EDO DRAM Interface Connection................15-74 15-64 EDO DRAM Single-Beat Read Access..............15-76 15-65 EDO DRAM Single-Beat Write Access ..............15-77 15-66 EDO DRAM Burst Read Access ................
Page 47 ILLUSTRATIONS Figure Page Title Number Number 18-4 CP Command Register (CPCR).................. 18-6 18-5 Dual-Port RAM Block Diagram ................. 18-9 18-6 Dual-Port RAM Memory Map.................. 18-10 18-7 RISC Timer Table RAM Usage................18-14 18-8 RISC Timer Command Register (TM_CMD) ............18-15 18-9 RISC Timer Event Register (RTER)/Mask Register (RTMR) .........
Page 48 ILLUSTRATIONS Figure Page Title Number Number 20-20 SI RAM Pointer Register (SIRP)................20-21 20-21 Bank-of-Clocks Selection Logic for NMSI .............. 20-23 20-22 Baud Rate Generator (BRG) Block Diagram ............20-24 20-23 Baud Rate Generator Configuration Registers (BRGCn)......... 20-25 21-1 SCC Block Diagram ....................21-2 21-2 GSMR_HÑGeneral SCC Mode Register (High Order) ..........
Page 49 ILLUSTRATIONS Figure Page Title Number Number 23-13 Nonsymmetrical Tx Clock Duty Cycle for Increased Performance ......23-20 23-14 HDLC Bus Transmission Line Configuration ............23-21 23-15 Delayed RTS Mode....................23-21 23-16 HDLC Bus TDM Transmission Line Configuration ..........23-22 24-1 LocalTalk Frame Format ....................
Page 50 ILLUSTRATIONS Figure Page Title Number Number 29-3 SMC Memory Structure....................29-5 29-4 SMC Function Code Registers (RFCR/TFCR) ............29-7 29-5 SMC UART Frame Format ..................29-10 29-6 SMC UART Receive BD (RxBD)................29-14 29-7 SMC UART Receiving using RxBDs ..............29-16 29-8 SMC UART Transmit BD (TxBD)................
Page 51 ILLUSTRATIONS Figure Page Title Number Number 31-14 I2C Transmit Buffer Descriptor (TxBD) ..............31-14 32-1 PIP Block Diagram ..................... 32-2 32-2 PIP Function Code Register (PFCR) ................32-4 32-3 Status Mask Register (SMASK) ................. 32-5 32-4 Control Character Table, RCCM, and RCCR............. 32-7 32-5 PIP Configuration Register (PIPC)................
Page 52 ILLUSTRATIONS Figure Page Title Number Number 33-21 Port D Data Register (PDDAT) ................33-23 33-22 Port D Data Direction Register (PDDIR) ..............33-24 33-23 Port D Pin Assignment Register (PDPAR)............... 33-24 34-1 MPC857T Interrupt Structure ..................34-2 34-2 Interrupt Request Masking..................34-4 34-3 CPM Interrupt Configuration Register (CICR) ............
Page 53 ILLUSTRATIONS Figure Page Title Number Number 39-4 APC Scheduling Tables .................... 39-11 39-5 PHY Transmit Queue....................39-11 39-6 Example of Three APC Priority Levels Combining APC Scheduling Tables and APC PTP queues ..................39-17 40-1 ATM Interrupt Queue ....................40-1 40-2 UTOPIA Event Register (IDSR1) and Mask Register (IDMR1) .......
Page 54 ILLUSTRATIONS Figure Page Title Number Number 44-3 Load/Store Support General Structure..............44-13 44-4 Partially Supported Watchpoints/Breakpoint Example ..........44-17 44-5 Functional Diagram of the MPC857T Debug Mode Support........44-20 44-6 Debug Mode Logic Diagram ..................44-21 44-7 Debug Mode Reset Configuration Timing Diagram ..........44-22 44-8 Development Port/BDM Connector Pinout Options ..........
Page 55 TABLES Table Page Title Number Number MPC857T Internal Memory Map ................. 2-1 Static Branch Prediction ..................... 3-10 Bus Cycles Needed for Single-Register Load/Store Accesses ........3-14 UISA-Level Features ....................3-16 VEA-Level Features ....................3-17 OEA-Level Features ....................3-18 User-Level PowerPC Registers..................4-2 User-Level PowerPC SPRs...................
Page 56 TABLES Table Page Title Number Number 5-20 System Linkage Instructions..................5-22 5-21 Move to/from Machine State Register Instructions ............ 5-22 5-22 Move to/from Special-Purpose Register Instructions ..........5-22 Offset of First Instruction by Exception Type .............. 6-2 Instruction-Related Exception Detection Order............6-4 Exception Priority ......................
Page 57 TABLES Table Page Title Number Number 8-11 MD_TWC Field Descriptions..................8-19 8-12 MI_RPN Field Descriptions ..................8-21 8-13 MD_RPN Field Descriptions..................8-22 8-14 M_TWB Field Descriptions..................8-23 8-15 M_CASID Field Descriptions..................8-23 8-16 MI_AP/MD_AP Field Descriptions ................8-24 8-17 MI_CAM Field Descriptions ..................8-25 8-18 MI_RAM0 Field Descriptions ..................
Page 58 TABLES Table Page Title Number Number 11-3 Hard Reset Configuration Word Field Descriptions........... 11-9 12-1 Signal Descriptions ....................12-5 12-2 Configuration-Dependent Signal Behavior during Reset ......... 12-23 12-3 Active Pull-Up Resistors Enabled as Outputs ............12-24 12-4 TCK/DSCK and TDI/DSDI Connection Based on MPC857T Revision....12-26 12-5 General Signal Behavior during Reset..............
Page 59 TABLES Table Page Title Number Number 16-1 PCMCIA Cycle Control Signals................. 16-3 16-2 PCMCIA Input Port Signals ..................16-4 16-3 PCMCIA Output Port Signals..................16-5 16-4 Other PCMCIA Signals ....................16-5 16-5 Host Programming for Memory Cards ............... 16-6 16-6 Host Programming For I/O Cards................
Page 60 TABLES Table Page Title Number Number 20-6 SICMR Field Descriptions..................20-20 20-7 SISTR Field Descriptions ..................20-20 20-8 SIRP Field Descriptions.................... 20-21 20-9 SIRP Pointer Values ....................20-22 20-10 BRGCn Field Descriptions ..................20-26 20-11 Typical Baud Rates for Asynchronous Communication .......... 20-27 21-1 GSMR_H Field Descriptions..................
Page 61 TABLES Table Page Title Number Number 25-6 Receive Errors......................25-9 25-7 SCCE/SCCM Field Descriptions................25-10 25-8 Asynchronous HDLC SCCS Field Descriptions ............25-11 25-9 PSMR Field Descriptions ..................25-11 25-10 Asynchronous HDLC RxBD Status and Control Field Descriptions ....... 25-12 25-11 Asynchronous HDLC TxBD Status and Control Field Descriptions .......
Page 62 TABLES Table Page Title Number Number 29-4 SMC UART-Specific Parameter RAM Memory Map ..........29-11 29-5 Transmit Commands....................29-12 29-6 Receive Commands ....................29-13 29-7 SMC UART Errors ....................29-14 29-8 SMC UART RxBD Status and Control Field Descriptions........29-15 29-9 SMC UART TxBD Status and Control Field Descriptions ........
Page 63 TABLES Table Page Title Number Number 32-5 Control Character Table, RCCM, and RCCR Descriptions ........32-7 32-6 PIPC Field Descriptions....................32-8 32-7 PIPE Field Descriptions.................... 32-10 32-8 PTPR Field Descriptions ..................32-10 32-9 PIP TxBD Status and Control Field Descriptions............. 32-12 32-10 PIP RxBD Status and Control Field Descriptions ............
Page 64 TABLES Table Page Title Number Number 36-2 ATM TxBD Field Descriptions .................. 36-8 36-3 RCT Field Descriptions .................... 36-11 36-4 PTP RCT Field Descriptions ..................36-14 36-5 TCT Field Descriptions..................... 36-17 36-6 PTP TCT Field Descriptions..................36-20 36-7 TCTE Field Descriptions ..................36-23 37-1 Serial ATM and UTOPIA Interface Parameter RAM Map ........
Page 65 TABLES Table Page Title Number Number 43-1 FEC Signal Descriptions................... 43-11 43-2 FEC Parameter RAM Memory Map................. 43-13 43-3 ADDR_LOW Field Descriptions................43-15 43-4 ADDR_HIGH Field Descriptions................43-16 43-5 HASH_TABLE_HIGH Field Descriptions .............. 43-17 43-6 HASH_TABLE_LOW Field Descriptions ............... 43-17 43-7 R_DES_START Field Descriptions .................
Page 66 TABLES Table Page Title Number Number 44-13 Debug Instructions/Data Shifted Into Development Port Shift Register ....44-33 44-14 MPC857T-Specific Development Support and Debug SPRs........44-36 44-15 Development Support/Debug Registers Protection ..........44-37 44-16 CMPAÐCMPD Field Descriptions ................44-37 44-17 CMPEÐCMPF Field Descriptions ................44-38 44-18 CMPGÐCMPH Field Descriptions ................
Page 67 TABLES Table Page Title Number Number D-12 Floating-Point Status and Control Register Instructions6 ......... D-20 D-13 Integer Load Instructions ................... D-21 D-14 Integer Store Instructions................... D-22 D-15 Integer Load and Store with Byte-Reverse Instructions ..........D-22 D-16 Integer Load and Store Multiple Instructions ............D-22 D-17 Integer Load and Store String Instructions ..............
Page 68 TABLES Table Page Title Number Number lxviii MPC857T PowerQUICC User’s Manual...
Page 69 About This Book The primary objective of this manual is to help communications system designers build systems using the Motorola MPC857T and to help software designers provide operating systems and user-level applications to take fullest advantage of the MPC857T. Although this book describes aspects regarding the PowerPCª architecture that are critical for understanding the MPC857T core, it does not contain a complete description of the architecture.
Page 70 Organization Following is a summary and a brief description of the chapters of this manual: ¥ Part I, ÒOverview,Ó provides a high-level description of the MPC857TMPC857T, describing general operation and listing basic features. Ñ Chapter 1, ÒMPC857T Overview, Ó provides a high-level description of MPC857T functions and features.
Page 71 Ñ Chapter 11, ÒReset,Ó describes the behavior of the MPC857T at reset and start-up. ¥ Part IV, ÒThe Hardware Interface,Ó describes external signals, clocking, memory control, and power management of the MPC857T. Ñ Chapter 12, ÒExternal Signals,Ó provides a detailed description of the external signals that comprise the MPC857T external interface.
Page 72 Ñ Chapter 23, ÒSCC HDLC Mode,Ó describes the MPC857T implementation of HDLC protocol. Ñ Chapter 24, ÒSCC AppleTalk Mode,Ó describes the MPC857T implementation of AppleTalk, a set of protocols developed by Apple Computer, Inc. to provide a LAN service between Macintosh computers and printers. Ñ...
Page 73 ¥ Part VI, ÒAsynchronous Transfer Mode (ATM),Ó describes the MPC857T ATM implementation. It consists of the following chapters: Ñ Chapter 35, ÒATM Overview,Ó gives a high-level description of the MPC857T ATM implementation, which adds major new features available in enhanced SAR (ESAR) mode, including multiple APC priority levels, port-to-port switching, simultaneous MII (100Base-T) and UTOPIA (half-duplex) capability, relocatable parameter RAM for both SPI and I...
Page 74 Ñ Chapter 45, ÒIEEE 1149.1 Test Access Port,Ó describes the dedicated user-accessible test access port (TAP), which is fully compatible with the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. ¥ Appendix A, ÒByte Ordering,Ó discusses the MPC857T implementation of little- and big-endian byte mapping.
Page 75 Ñ PowerPC Microprocessor Family: The Programming Environments, Rev 1 (Motorola order #: MPCFPE/AD) Ñ PowerPC Microprocessor Family: The Programming Environments for 32-Bit Microprocessors, Rev. 1 (Motorola order #: MPCFPE32B/AD) • PowerPC Microprocessor Family: The Bus Interface for 32-Bit Microprocessors (Motorola order #: MPCBUSIF/AD) provides a detailed functional description of the 60x bus interface, as implemented on the PowerPC 601ª, 603, and 604 family of PowerPC microprocessors.
Page 76 In certain contexts, such as in a signal encoding or a bit Þeld, indicates a donÕt care. Used to express an undeÞned numerical value ¬ NOT logical operator & AND logical operator OR logical operator Acronyms and Abbreviations Table i contains acronyms and abbreviations used in this document. Note that the meanings for some acronyms (such as SDR1 and DSISR) are historical, and the words for which an acronym stands may not be intuitively obvious.
Page 77 Table i. Acronyms and Abbreviated Terms (Continued) Term Meaning DRAM Dynamic random access memory DSISR Register used for determining the source of a DSI exception DTLB Data translation lookaside buffer Effective address EEST Enhanced Ethernet serial transceiver EPROM Erasable programmable read-only memory Floating-point register FPSCR Floating-point status and control register...
Page 78 Table i. Acronyms and Abbreviated Terms (Continued) Term Meaning Most-signiﬁcant bit Machine state register Not a number Next instruction address NMSI Nonmultiplexed serial interface No-op No operation Operating environment architecture Open systems interconnection Peripheral component interconnect PCMCIA Personal Computer Memory Card International Association Processor identiﬁcation register Primary rate interface Processor version register...
Page 79 Table i. Acronyms and Abbreviated Terms (Continued) Term Meaning Test access port Time base register Time-division multiplexed Translation lookaside buffer Time-slot assigner Transmit UART Universal asynchronous receiver/transmitter UIMM Unsigned immediate value UISA User instruction set architecture User-programmable machine USART Universal synchronous/asynchronous receiver/transmitter Virtual address Virtual environment architecture Register used primarily for indicating conditions such as carries and overﬂows for integer operations...
Page 80 Table iii describes instruction Þeld notation conventions used in this manual. Table iii. Instruction Field Conventions The Architecture Speciﬁcation Equivalent to: BA, BB, BT crbA, crbB, crbD (respectively) BF, BFA crfD, crfS (respectively) RA, RB, RT, RS rA, rB, rD, rS (respectively) SIMM UIMM /, //, ///...
Page 81 Part I Overview Intended Audience Part I is intended for anyone who needs a high-level understanding of the MPC857T. Contents Part I provides an overview of the features and functions of the MPC857T. It includes the following chapters: ¥ Chapter 1, ÒMPC857T Overview, Ó provides a high-level description of MPC857T functions and features.
Page 82 appear in brackets. For example, MSR[LE] refers to the little-endian mode enable bit in the machine state register. In certain contexts, such as in a signal encoding or a bit Þeld, indicates a donÕt care. Indicates an undeÞned numerical value Acronyms and Abbreviations Table i contains acronyms and abbreviations that are used in this document.
Page 83 Table i. Acronyms and Abbreviated Terms (Continued) Term Meaning Operating environment architecture Open systems interconnection Peripheral component interconnect PCMCIA Personal Computer Memory Card International Association RISC Reduced instruction set computing RTOS Real-time operating system Receive Serial communications controller SDLC Synchronous data link control SDMA Serial DMA Serial interface...
Page 84 I-iv MPC857T PowerQUICC User’s Manual...
Page 85: Mpc857T Overview
Chapter 1 MPC857T Overview MPC857T PowerPCª Quad Integrated Communications Controller (PowerQUICCª) is a versatile one-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications. It particularly excels in both communications and networking systems. Unless otherwise speciÞed, the PowerQUICC unit is referred to as the MPC857T in this manual.
Page 86: Features
Features 1.1 Features The following list summarizes the key MPC857T features: ¥ Embedded PowerPC core ¥ Single-issue, 32-bit version of the core (compatible the PowerPC architecture deÞnition) with 32, 32-bit general-purpose registers (GPRs) Ñ The core performs branch prediction with conditional prefetch, without conditional execution Ñ...
Page 87 Features ¥ Memory controller (eight banks) Ñ Contains complete dynamic RAM (DRAM) controller Ñ Each bank can be a chip select or RAS to support a DRAM bank Ñ Up to 30 wait states programmable per memory bank Ñ Glueless interface to DRAM, SIMMS, SRAM, EPROMs, ßash EPROMs, and other memory devices.
Page 88 Features ¥ Communications processor module (CPM) Ñ RISC controller Ñ Communication-speciÞc commands (for example, GRACEFUL STOP TRANSMIT , and ENTER HUNT MODE RESTART TRANSMIT Ñ Up to 384 buffer descriptors (BDs) Ñ Supports continuous mode transmission and reception on all serial channels Ñ...
Page 89 Features ¥ One SPI (serial peripheral interface) Ñ Supports master and slave modes Ñ Supports multimaster operation on the same bus ¥ One I C (inter-integrated circuit) port Ñ Supports master and slave modes Ñ Multiple-master environment support ¥ Time-slot assigner (TSA) Ñ...
Page 90 Features The MPC857T is comprised of three modules that each use the 32-bit internal bus: the PowerPC core, the system integration unit (SIU), and the communication processor module (CPM). The MPC857T block diagram is shown in Figure 1-1. 4-Kbyte Instruction System Interface Unit (SIU) Instruction Cache Unified...
Page 91: Embedded Powerpc Core
Embedded PowerPC Core 1.2 Embedded PowerPC Core The MPC857T integrates an embedded PowerPC core with high-performance, low-power peripherals to extend the Motorola Data Communications family of embedded processors farther into high-end communications and networking products. The core is compliant with the UISA (user instruction set architecture) portion of the PowerPC architecture.
Page 92: System Interface Unit (Siu)
System Interface Unit (SIU) 1.3 System Interface Unit (SIU) The SIU on the MPC857T integrates general-purpose features useful in almost any 32-bit processor system, enhancing the performance of the system integration module (SIM) on the MC68360 QUICC device. Dynamic bus sizing allows 8-, 16-, and 32-bit peripherals and memory to exist in the 32-bit system bus mode.
Page 93: Communications Processor Module (Cpm)
Communications Processor Module (CPM) ¥ Doze mode disables core functional units other than the time base decrementer, PLL, memory controller, RTC, and places the CPM in low-power standby mode. ¥ Sleep mode disables everything except the RTC and PIT, leaving the PLL active for quick wake-up.
Page 94: Atm Capabilities
ATM Capabilities 1.7 ATM Capabilities The MPC857T can be used as an adaptable ATM controller suited for a variety of applications, including the following: ¥ ATM line card controllers ¥ ATM-to-WAN interworking, including frame relay, T1/E1 circuit emulation service (CES), and xDSL applications ¥...
Page 95: Memory Map
Chapter 2 Memory Map Each memory resource in the MPC857T is mapped within a contiguous block of 16 Kbyte memory. The location of this block within the global 4-Gbyte physical memory space can be mapped on 64-Kbyte resolution through an implementation-speciÞc special-purpose register (SPR) called the internal memory map register (IMMR).
Page 96 Table 2-1. MPC857T Internal Memory Map (Continued) Offset Name Size Section/Page PBR4—PCMCIA interface base register 4 32 bits 16.4.5/-12 POR4—PCMCIA interface option register 4 32 bits 16.4.6/-12 PBR5—PCMCIA interface base register 5 32 bits 16.4.5/-12 POR5—PCMCIA interface option register 5 32 bits 16.4.6/-12 PBR6—PCMCIA interface base register 6...
Page 97 Table 2-1. MPC857T Internal Memory Map (Continued) Offset Name Size Section/Page 140–163 Reserved 36 bytes — MAR—Memory address register 32 bits 15.4.7/-17 MCR—Memory command register 32 bits 15.4.5/-15 16C–16F Reserved 4 bytes — MAMR—Machine A mode register 32 bits 15.4.4/-13 MBMR—Machine B mode register 32 bits 15.4.4/-13...
Page 98 Table 2-1. MPC857T Internal Memory Map (Continued) Offset Name Size Section/Page TBSCRK—Timebase status and control register 32 bits 10.4.5/-10 TBREFAK—Timebase reference register A key 32 bits 10.4.5/-10 TBREFBK—Timebase reference register B key 32 bits 10.4.5/-10 TBK—Timebase/decrementer register key 32 bits 10.4.5/-10 310–31F Reserved...
Page 99 Table 2-1. MPC857T Internal Memory Map (Continued) Offset Name Size Section/Page SDAR—SDMA address register 32 bits 19.2.4/-5 SDSR—SDMA status register 8 bits 19.2.2/-4 909–90B Reserved 3 bytes — SDMR—SDMA mask register 8 bits 19.2.3/-5 90D–90F Reserved 3 bytes — IDSR1—IDMA1 status register 8 bits 19.3.9.2/-19 911–913...
Page 100 Table 2-1. MPC857T Internal Memory Map (Continued) Offset Name Size Section/Page PDDAT—Port D data register 16 bits 33.5.2.1/-22 978–97F UTMODE—UTOPIA mode register 4 bytes 42.2/-1 97–97F Reserved bytes — CPM General-Purpose Timers TGCR—Timer global conﬁguration register 16 bits 17.2.3.1/-8 982–98F Reserved 14 bytes —...
Page 101 Table 2-1. MPC857T Internal Memory Map (Continued) Offset Name Size Section/Page RCTR2—RISC controller trap register 2 16 bits Used only by optional RAM microcode RCTR3—RISC controller trap register 3 16 bits Used only by optional RAM microcode RCTR4—RISC controller trap register 4 16 bits Used only by optional RAM microcode 9D4–9D5...
Page 102 Table 2-1. MPC857T Internal Memory Map (Continued) Offset Name Size Section/Page A84–A85 Reserved 2 bytes — SMCE1—SMC1 event register 8 bits 29.3.12/-18 (UART) 29.4.11/-29 (Transparent) 29.5.9/-36 (GCI) A87–A89 Reserved 3 bytes — SMCM1—SMC1 mask register 8 bits 29.3.12/-18 (UART) 29.4.11/-29 (Transparent) 29.5.9/-36 (GCI) A8B–A91 Reserved...
Page 103 Table 2-1. MPC857T Internal Memory Map (Continued) Offset Name Size Section/Page Serial Interface (SI) SIMODE—SI mode register 32 bits 20.2.4.2/-13 SIGMR—SI global mode register 8 bits 20.2.4.1/-12 Reserved 8 bits — SISTR—SI status register 8 bits 20.2.4.5/-20 SICMR—SI command register 8 bits 20.2.4.4/-19 AE8–AEB...
Page 104 Table 2-1. MPC857T Internal Memory Map (Continued) Offset Name Size Section/Page F88-1FFF Reserved 4,215 bytes Dual-Port RAM (DPRAM) 2000–2FFF Dual-port system RAM 4,096 bytes 18.6.1/-10 3000–3BFF Dual-port system RAM expansion 3,072 bytes 18.6.1/-10 3C00–3FFF PRAM—Dual-port parameter RAM 1,024 bytes 18.6.3/-11 2-10 MPC857T PowerQUICC User’s Manual...
Page 105: Powerpc Microprocessor Module
Part II PowerPC Microprocessor Module Intended Audience Part II is intended for users who need to understand the programming model of the embedded microprocessor. It assumes some familiarity with RISC architectures. Contents Part II describes the PowerPC microprocessor embedded in the MPC857T. It provides detailed information on the registers and instructions that are implemented, the memory management unit (MMU), cache model, exception model, and an overview of instruction timing.
Page 106 ¥ Chapter 8, ÒMemory Management UnitÓ describes how the PowerPC MMU model is implemented on the MPC857T. Although the MPC857T MMU is based on the PowerPC MMU model, it differs greatly in many respects, which are described in this chapter. ¥...
Page 107 ¥ PowerPC Microprocessor Family: The Programmer’s Pocket Reference Guide (Motorola order #: MPCPRGREF/D). This feedlot card provides an overview of the PowerPC registers, instructions, and exceptions for 32-bit implementations. ¥ Application notesÑThese short documents contain useful information about speciÞc design issues useful to programmers and engineers working with PowerPC processors.
Page 108 Acronyms and Abbreviations Table i contains acronyms and abbreviations that are used in this document. Note that the meanings for some acronyms (such as SDR1 and DSISR) are historical, and the words for which an acronym stands may not be intuitively obvious. Table i.
Page 109 Table i. Acronyms and Abbreviated Terms (Continued) Term Meaning Most-signiﬁcant byte Most-signiﬁcant bit Machine state register Not a number No-op No operation Operating environment architecture Peripheral component interconnect Processor version register RISC Reduced instruction set computing RTOS Real-time operating system RWITM Read with intent to modify Receive...
Page 110 PowerPC Architecture Terminology Conventions Table ii lists certain terms used in this manual that differ from the architecture terminology conventions. Table ii. Terminology Conventions The Architecture Speciﬁcation This Manual Data storage interrupt (DSI) DSI exception Extended mnemonics Simpliﬁed mnemonics Instruction storage interrupt (ISI) ISI exception Interrupt Exception...
Page 111 Part II. PowerPC Microprocessor Module Part II-vii...
Page 112 Part II-viii MPC857T PowerQUICC User’s Manual...
Page 113: The Powerpc Core
Chapter 3 The PowerPC Core This chapter provides an overview of the MPC857T core, summarizing topics described in further detail in subsequent chapters in Part II. This chapter describes the functional speciÞcations of the core. It is based on the PowerPC Microprocessor Family: The Programming Environments for 32-Bit Microprocessors, which provides a more in-depth discussion of issues related to the 32-bit portion of the PowerPC architecture.
Page 114 PowerPC Architecture Overview process technology, compiler design, and reduced instruction set computing (RISC) microprocessor design to provide software compatibility across a diverse family of implementations, primarily single-chip microprocessors, intended for a wide range of systems, including battery-powered personal computers; embedded controllers; high-end scientiÞc and graphics workstations;...
Page 115: Levels Of The Powerpc Architecture
PowerPC Architecture Overview ¥ Support for 64-bit addressing. The architecture supports both 32-bit or 64-bit implementations. This document describes the 32-bit portion of the PowerPC architecture. For information about the 64-bit architecture, see PowerPC Microprocessor Family: The Programming Environments. 3.2.1 Levels of the PowerPC Architecture The PowerPC architecture is deÞned in three levels that correspond to three programming environments, roughly described from the most general, user-level instruction set environment, to the more speciÞc, operating environment.
Page 116: Features
Features the UISA and the VEA levels. For a more detailed discussion of the characteristics of the PowerPC architecture, see the Programming Environments Manual. For details regarding the MPC857T as a PowerPC implementation, see Section 3.7, ÒThe MPC857T and the PowerPC Architecture.Ó 3.3 Features Figure 3-1 shows the basic features of the MPC857T.
Page 117 Features 32-Bit (One Instruction) 32-Bit Sequential Completion Branch Fetcher Queue Processing Unit 32-Bit Instruction Queue INSTRUCTION UNIT 32-Bit (One Instruction) One Instruction Retired per Clock 32-Bit 32-Bit Integer GPR File Unit (32-Entry) L-Bus Load/Store ⁄ Unit (LSU) • • • Performs Calculation Data...
Page 118: Basic Structure Of The Core
Basic Structure of the Core The following is a list of the coreÕs main features: ¥ 32-bit PowerPC architecture features Ñ User-level instruction set (not including ßoating-point instructions) Ñ Thirty-two, 32-bit general-purpose registers (GPRs) Ñ Registers required to support PowerPC user-level instruction set (except ßoating-point instructions).
Page 119: Instruction Flow
Basic Structure of the Core 3.4.1 Instruction Flow As many as one instruction per clock cycle is fetched into the four-entry instruction queue (IQ). The branch processing unit (BPU) predicts the outcome of branch instructions and in some cases, resolves whether the branch is taken. Figure 3-2 shows general instruction ßow.
Page 120: Basic Instruction Pipeline
Basic Structure of the Core 3.4.2 Basic Instruction Pipeline Figure 3-3 shows instruction pipeline timing, showing how by distributing the processes required to fetch, execute, and retire an instruction into stages, multiple instructions can be processed during a single clock cycle. Gclk1 addic mulli...
Page 121 Basic Structure of the Core Instruction Memory System 32-Bit Instruction Address Generator Instruction Buffer 32-Bit Branch Instruction Read/Write Condition Queue (4) CC Unit Busses Evaluation (IQ) 32-Bit Execution Units and Registers Files Figure 3-4. Sequencer Data Path The instruction unit executes branches in parallel with those instructions that must be dispatched to an execution unit.
Page 122: Dispatching Instructions
Register Set Table 3-1. Static Branch Prediction Branch Type Default Prediction (y=0) Modiﬁed Prediction (y=1) BC with negative offset Taken Fall through BC with positive offset Fall through Taken BCLR or BCCTR (LR or CTR) address ready Fall through Taken BCLR or BCCTR (LR or CTR) address not ready Wait Wait...
Page 123: Branch Processing Unit
Execution Units 3.6.1 Branch Processing Unit The branch processing unit differs from the other execution units in that it examines branch instructions while they are in the IQ. Other instructions are dispatched to the IU and LSU from IQ0. For details about the performance of various instructions, see Table 3-1. The core supports the UISA-deÞned static branch prediction.
Page 124 Execution Units The following lists the LSUÕs main features: ¥ All instructions implemented in hardware, including unaligned, string, and multiple accesses ¥ Two-entry load/store instruction address queue ¥ Pipelined operation. The LSU pipelines load accesses. Individual cache accesses of all multiple-register instructions and unaligned accesses are pipelined into the data cache interface.
Page 125: Executing Load/Store Instructions
Execution Units 3.6.3.1 Executing Load/Store Instructions When load or store instructions are dispatched, the LSU determines if all of the operands are available. These operands include the following: ¥ Address register operands ¥ Source data register operands (for store instructions) ¥...
Page 126: Nonspeculative Load Instructions
Execution Units 3.6.3.4 Nonspeculative Load Instructions Load instructions targeted at nonspeculative memory are identiÞed as nonspeculative one clock cycle after the previous load/store bus cycle ends, only if all prior instructions have Þnished without an exception. The nonspeculative identiÞcation relates to the state of the cycleÕs associated instruction. For lmw, although the accesses are pipelined into the bus, they are all marked as nonspeculative because the instruction is nonspeculative.
Page 127: Atomic Update Primitives
The MPC857T and the PowerPC Architecture 3.6.3.6 Atomic Update Primitives The lwarx and stwcx. instructions are atomic update primitives and are used to set and clear memory reservations. Reservation accesses made by the same processor are implemented by the LSU. The external bus interface implements memory reservations as they relate to accesses made by external bus devices.
Page 128 The MPC857T and the PowerPC Architecture Table 3-3 summarizes MPC857T features with respect to the UISA deÞnition. Table 3-3. UISA-Level Features Functionality Description Reserved ﬁelds Reserved ﬁelds in instructions are described under the speciﬁc instruction deﬁnition in Chapter 5, “MPC857T Instruction Set.” Unless otherwise stated, instruction ﬁelds marked I, II, and III are discarded during decoding.
Page 129 The MPC857T and the PowerPC Architecture Table 3-3. UISA-Level Features (Continued) Functionality Description Integer load/ For these types of instructions, EA must be a multiple of four. If it is not, the system alignment store multiple error handler is invoked. For an lmw instruction (if rA is in the range of registers to be loaded), the instructions instruction completes normally.
Page 130 The MPC857T and the PowerPC Architecture Table 3-4. VEA-Level Features (Continued) Functionality Description Memory The MPC857T interprets cache control instructions as if they pertain only to the MPC857T cache. control These instructions do not broadcast. Any bus activity caused by these instructions results from an instructions operation performed on the MPC857T cache and not because of the instruction itself.
Page 131 The MPC857T and the PowerPC Architecture Table 3-5. OEA-Level Features (Continued) Functionality Description Address If address translation is disabled (MSR[IR] = 0 for instruction accesses or MSR[DR] = 0 for data translation accesses), the EA is treated as the physical address and is passed directly to the memory subsystem.
Page 132 The MPC857T and the PowerPC Architecture 3-20 MPC857T PowerQUICC User’s Manual...
Page 133: Powerpc Core Register Set
Chapter 4 PowerPC Core Register Set This chapter describes the software-accessible registers implemented on the MPC857T. These include registers that are deÞned by the PowerPC architecture and registers that are speciÞc to the MPC857T. This section does not include registers that are part of the communication processor module (CPM);...
Page 134: Powerpc User-Level Register Bit Assignments
MPC857T Register Implementation 4.1.1 PowerPC Registers—User Registers The MPC857T implements the user-level registers deÞned by the PowerPC architecture except those required for supporting ßoating-point operations (the ßoating-point register Þle (FPRs) and the ßoating-point status and control register (FPSCR)). User-level, PowerPC registers are listed in Table 4-1 and Table 4-2. Table 4-2 lists user-level special-purpose registers (SPRs).
Page 135: Condition Register (Cr)
MPC857T Register Implementation 4.1.1.1.1 Condition Register ( The condition register (CR) is a 32-bit register that reßects the result of certain operations and provides a mechanism for testing and branching. The bits in the CR are grouped into eight 4-bit Þelds, CR0ÐCR7, as shown in Figure 4-1. Figure 4-1.
Page 136: Xer
MPC857T Register Implementation 4.1.1.1.3 XER Figure 4-2 shows XER bit assignments. Settings are based on the Þnal result produced by executing an instruction. Field — Reset 0000_0000_0000_0000 Field — BCNT Reset 0000_0000_0000_0000 Figure 4-2. XER Register XER bits are described in Table 4-4. Table 4-4.
Page 137 MPC857T Register Implementation 4.1.2 PowerPC Registers—Supervisor Registers All supervisor-level registers implemented on the MPC857T are SPRs, except for the machine state register (MSR), described in Table 4-5. Table 4-5. Supervisor-Level PowerPC Registers Description Name Comments Serialize Access Machine state register See Section 4.1.2.3.1, “Machine State Register (MSR).”...
Page 138: Dar, Dsisr, And Bar Operation
MPC857T Register Implementation 4.1.2.1 DAR, DSISR, and BAR Operation The LSU updates the DAR, DSISR, and BAR when an exception is taken. ¥ When a bus error occurs, the data address register (DAR) is loaded with the effective address. For instructions that generate multiple accesses, the effective address of the Þrst offending tenure is loaded.
Page 139: Machine State Register (Msr)
MPC857T Register Implementation 4.1.2.3.1 Machine State Register (MSR) The 32-bit machine state register (MSR) is used to conÞgure such parameters as the privilege level, whether translation is enabled, and the endian-mode. It can be read by the mfmsr instruction and modiÞed by the mtmsr, sc, and rﬁ instructions. Field —...
Page 140: Processor Version Register
MPC857T Register Implementation Table 4-8. MSR Field Descriptions (Continued) Bit(s) Name Description Machine check enable 0 Machine check exceptions are disabled. 1 Machine check exceptions are enabled. — Reserved Single-step trace enable (Optional) 0 The processor executes instructions normally. 1 A single-step trace exception is generated when the next instruction executes successfully. Note: If the function is not implemented, SE is treated as reserved.
Page 141: Mpc857T-Specific Sprs
MPC857T Register Implementation 4.1.3 MPC857T-Speciﬁc SPRs Table 4-2 and Table 4-9 list SPRs speciÞc to the MPC857T. Debug registers, which have additional protection, are described in Chapter 44, ÒSystem Development and Debugging.Ó Supervisor-level registers are described in Table 4-9. Table 4-9. MPC857T-Specific Supervisor-Level SPRs SPR Number Name Comments...
Page 142 MPC857T Register Implementation Table 4-9. MPC857T-Specific Supervisor-Level SPRs (Continued) SPR Number Name Comments Serialize Access Decimal SPR[5–9] SPR[0–4] 11001 10010 MI_RAM1 Section 8.8.13, “DMMU RAM Entry Write (as a store) Read Register 1 (MD_RAM1)” 11000 11000 MD_CTR Section 8.8.2, “DMMU Control Write (as a store) Register (MD_CTR).”...
Page 143: Accessing Sprs
MPC857T Register Implementation Table 4-10. MPC857T-Specific Debug-Level SPRs (Continued) SPR Number Name Serialize Access Decimal SPR[5–9] SPR[0–4] 00100 10101 Fetch sync on write 00100 10110 COUNTA Fetch sync on write 00100 10111 COUNTB Fetch sync on write 00100 11000 CMPE Write: Fetch sync Read: Sync relative to load/store operations 00100...
Page 144: Register Initialization At Reset
Register Initialization at Reset 4.2 Register Initialization at Reset This section describes how basic registers are set under reset conditions, other register settings are described in Chapter 7, ÒInstruction and Data Caches,Ó and Chapter 8, ÒMemory Management Unit.Ó A system reset interrupt occurs when a nonmaskable interrupt is generated either by the software watchdog timer or the assertion of IRQ0.
Page 145: Mpc857T Instruction Set
Chapter 5 MPC857T Instruction Set This chapter describes the PowerPC instructions implemented by the MPC857T. These instructions are organized by the level of architecture in which they are implementedÑUISA, VEA, and OEA. These levels are described in Section 3.2.1, ÒLevels of the PowerPC Architecture.Ó...
Page 146: Instruction Set Summary
Instruction Set Summary Table 5-1. Memory Operands Operand Length Addr[28–31] If Aligned Byte 8 bits xxxx Half word 2 bytes xxx0 Word 4 bytes xx00 Double word 8 bytes x000 Quad word 16 bytes 0000 Note: An “x” in an address bit position indicates that the bit can be 0 or 1 independent of the state of other bits in the address.
Page 147: Classes Of Instructions
Instruction Set Summary ¥ Memory synchronization instructionsÑThese instructions are used for memory synchronizing. See Sections 5.2.4.6 and 5.2.5.2 for more information. ¥ Memory control instructionsÑThese instructions provide control of caches, and TLBs. For more information, see Sections 5.2.5.3 and 5.2.6.3. ¥...
Page 148: Definition Of Boundedly Undefined
Instruction Set Summary 5.2.1.1 Deﬁnition of Boundedly Undeﬁned If instructions are encoded with incorrectly set bits in reserved Þelds, the results on execution can be said to be boundedly undeÞned. If a user-level program executes the incorrectly coded instruction, the resulting undeÞned results are bounded in that a spurious change from user to supervisor state is not allowed, and the level of privilege exercised by the program in relation to memory access and other system resources cannot be exceeded.
Page 149 Instruction Set Summary The following primary opcodes have unused extended opcodes. 17, 19, 31, 59, 63 (primary opcodes 30 and 62 are illegal for all 32-bit implementations, but as 64-bit opcodes they have some unused extended opcodes) ¥ An instruction consisting entirely of zeros is guaranteed to be an illegal instruction. This increases the probability that an attempt to execute data or uninitialized memory invokes the system illegal instruction error handler (a program exception).
Page 150 Instruction Set Summary 5.2.2.2 Effective Address Calculation An effective address (EA) is the 32-bit sum computed by the processor when executing a memory access or branch instruction or when fetching the next sequential instruction. For a memory access instruction, if the sum of the effective address and the operand length exceeds the maximum effective address, the memory operand is considered to wrap around from the maximum effective address through effective address 0, as described in the following paragraphs.
Page 151 Instruction Set Summary 5.2.2.3.2 Execution Synchronization An instruction is execution synchronizing if all previously initiated instructions appear to have completed before the instruction is initiated or, in the case of the Synchronize (sync) and Instruction Synchronize (isync) instructions, before the instruction completes. For example, the Move to Machine State Register (mtmsr) instruction is execution synchronizing.
Page 152 Instruction Set Summary Programming Environments Manual. These categorizations are somewhat arbitrary and are provided for the convenience of the programmer and do not necessarily reßect the PowerPC architecture speciÞcation. Note that some of the instructions have the following optional features: ¥...
Page 153 Instruction Set Summary Table 5-2. Integer Arithmetic Instructions (Continued) Name Mnemonic Syntax Subtract from Minus One Extended subfme (subfme.subfmeosubfmeo.) rD,rA Add to Zero Extended addze (addze.addzeoaddzeo.) rD,rA Subtract from Zero Extended subfze (subfze.subfzeosubfzeo.) rD,rA Negate neg (neg.negonego.) rD,rA Multiply Low Immediate mulli rD,rA,SIMM Multiply Low...
Page 154 Instruction Set Summary 5.2.4.1.3 Integer Logical Instructions The logical instructions shown in Table 5-4 perform bit-parallel operations. Logical instructions with the CR update enabled and instructions andi. and andis. set CR Þeld CR0 to characterize the result of the logical operation. These Þelds are set as if the sign-extended low-order 32 bits of the result were algebraically compared to zero.
Page 155 Instruction Set Summary of the rotated data is placed into the target register, and if the mask bit is 0 the associated bit in the target register is unchanged), or ANDed with a mask before being placed into the target register. The integer rotate instructions are listed in Table 5-5. Table 5-5.
Page 156 Instruction Set Summary 5.2.4.2.2 Register Indirect Integer Load Instructions For integer load instructions, the byte, half word, or word addressed by the EA is loaded into rD. Many integer load instructions have an update form, in which rA is updated with the generated effective address.
Page 157 Instruction Set Summary Table 5-8. Integer Store Instructions Name Mnemonic Syntax Store Byte rS,d(rA) Store Byte Indexed stbx rS,rA,rB Store Byte with Update stbu rS,d(rA) Store Byte with Update Indexed stbux rS,rA,rB Store Half Word rS,d(rA) Store Half Word Indexed sthx rS,rA,rB Store Half Word with Update...
Page 158 Instruction Set Summary Manual for more information. Table 5-10 lists the integer load and store multiple instructions for the MPC857T. Table 5-10. Integer Load and Store Multiple Instructions Name Mnemonic Syntax Load Multiple Word rD,d(rA) Store Multiple Word stmw rS,d(rA) 5.2.4.2.6 Integer Load and Store String Instructions The integer load and store string instructions allow movement of data from memory to registers or from registers to memory without concern for alignment.
Page 159 Instruction Set Summary Some branch instructions can redirect instruction execution conditionally based on the value of bits in the CR. When the branch processor encounters one of these instructions, it scans the execution pipelines to determine whether an instruction in progress may affect the particular CR bit.
Page 160 Instruction Set Summary Table 5-12. Branch Instructions Name Mnemonic Syntax Branch b (bablbla) target_addr Branch Conditional bc (bcabclbcla) BO,BI,target_addr Branch Conditional to Link Register bclr (bclrl) BO,BI Branch Conditional to Count Register bcctr (bcctrl) BO,BI 5.2.4.3.3 Condition Register Logical Instructions Condition register logical instructions, shown in Table 5-13, and the Move Condition Register Field (mcrf) instruction are also deÞned as ßow control instructions.
Page 161 Instruction Set Summary 5.2.4.5 Processor Control Instructions Processor control instructions are used to read from and write to the condition register (CR), machine state register (MSR), and special-purpose registers (SPRs), and to read from the time base register (TBU or TBL). 5.2.4.5.1 Move to/from Condition Register Instructions Table 5-15 lists the instructions provided by the MPC857T for reading from or writing to the CR.
Page 162 Instruction Set Summary memory,Ó and Òfetch and add.Ó Examples of these semaphore operations can be found in Appendix E, ÒSynchronization Programming Examples,Ó in The Programming Environments Manual. The lwarx instruction must be paired with an stwcx. instruction with the same effective address used for both instructions of the pair. Note that the reservation granularity is 16 bytes.
Page 163 Instruction Set Summary The original purpose of the sync instruction was to synchronize coherent memory with other processors in a multiprocessor system; it makes sure that memory as seen by one processor is the same as memory seen by the other processors, and broadcasts a special signal to signal that the action is taking place.
Page 164 Instruction Set Summary Table 5-18 lists the VEA memory synchronization instructions for the MPC857T. Table 5-18. Memory Synchronization Instructions—VEA Mnemoni Name Syntax MPC857T Notes Enforce In-Order eieio — During execution, the LSU waits for previous accesses to terminate before Execution of I/O beginning accesses associated with load/store instructions after an eieio.
Page 165 Instruction Set Summary The instructions listed in Table 5-19 provide user-level programs the ability to manage on-chip caches. As with other memory-related instructions, the effect of the cache management instructions on memory are weakly ordered. If the programmer needs to ensure that cache or other instructions have been performed with respect to all other processors and system mechanisms, a sync instruction must be placed in the program following those instructions.
Page 166 Instruction Set Summary Table 5-20. System Linkage Instructions Name Mnemonic Syntax System Call — Return from Interrupt rﬁ — 5.2.6.2 Processor Control Instructions—OEA Processor control instructions are used to read from and write to the condition register (CR), machine state register (MSR), and special-purpose registers (SPRs), and to read from the time base register (TBU or TBL).
Page 167 Chapter 6 Exceptions Core exceptions can be generated when an exception condition occurs. Exception sources in the MPC857T include the following: ¥ External interrupt request ¥ Certain memory access conditions (protection faults and bus errors) ¥ Internal errors, such as an attempt to execute an unimplemented opcode ¥...
Page 168 Exceptions 6.1 Exceptions The OEA deÞnes a set of exceptions for PowerPC processors, some of which are optional. The following sections describe exceptions implemented on the MPC857T. Those deÞned by the OEA are described in Section 6.1.2, ÒPowerPC-DeÞned Exceptions.Ó Section 6.1.3, ÒImplementation-SpeciÞc Exceptions,Ó...
Page 169 Exceptions Table 6-1. Offset of First Instruction by Exception Type (Continued) Offset Exception Description 0x00800 Floating-point unavailable The MPC857T cannot generate a ﬂoating-point exception. Attempting to execute a ﬂoating-point instruction causes an implementation-speciﬁc software emulation exception (see Section 6.1.3.1, “Software Emulation Exception (0x01000)”) regardless of the setting of MSR[FP].
Page 170 Exceptions Table 6-2. Instruction-Related Exception Detection Order Number Exception Type Cause Trace Trace bit asserted ITLB miss Instruction MMU TLB miss ITLB error Instruction MMU protection/translation error Machine check Fetch error Debug instruction breakpoint Match detection Software emulation exception Attempt to invoke unimplemented feature Privileged instruction Attempt to execute privileged instruction in user mode Alignment...
Page 171 Exceptions begin fetching at 0x00100 after the associated reset actions. Table 6-4 shows register settings. Table 6-4. Register Settings after a System Reset Interrupt Exception Register Setting SRR0 Set to the EA of the next instruction of the interrupted process. SRR1 Saves the machine status prior to exceptions and to restore status when an rﬁ...
Page 172 Exceptions Table 6-5. Register Settings after a Machine Check Interrupt Exception (Continued) Register Setting DSISR Set when the load/store bus is used: 0–140 15–16Set to bits 29-30 of the instruction if X-form instruction and to 0b00 if D-form. 17 Set to bit 25 of the instruction if X-form instruction and to bit 5 if D-form. 18–21Set to bits 21-24 of the instruction if X-form instruction and to bits 1-4 if D-form.
Page 173 Exceptions System-level exception latency can be longer than the interval from B to E. If an instruction ahead of the exception-causing instruction also generates an exception, that exception is recognized Þrst. If it is important to minimize exception latency, exception handlers should save the machine context and reenable exceptions as quickly as possible so pending external exceptions are handled quickly.
Page 174 Exceptions The register settings for alignment exceptions are shown in Table 6-7. Table 6-7. Register Settings after an Alignment Exception Register Setting Description SRR0 Set to the effective address of the instruction that caused the exception. SRR1 Loaded with equivalent bits from the MSR 1–4 Cleared 5–9...
Page 175 Exceptions 6.1.2.7 Program Exception (0x00700) A program exception occurs when no higher priority exception exists and one or more of the following exception conditions, which correspond to bit settings in SRR1, occur during execution of an instruction: ¥ An lswx instruction for which rA or rB is in the range of registers to be loaded (may cause results that are boundedly undeÞned) ¥...
Page 176 Exceptions 6.1.2.8 Decrementer Exception (0x00900) A decrementer exception occurs when no higher priority exception exists, a decrementer exception condition occurs (for example, the decrementer register has completed decremented), and MSR[EE] = 1. The decrementer register counts down, causing an exception request when it passes through zero. A decrementer exception request remains pending until the decrementer exception is taken and then it is cancelled.
Page 177 Exceptions The system call exception causes the next instruction to be fetched from offset 0x00C00 from the physical base address indicated by the new setting of MSR[IP]. As with most other exceptions, this exception is context-synchronizing. Refer to Section 5.2.2.3.1, ÒContext Synchronization,Ó...
Page 178 Exceptions 6.1.2.11 Floating-Point Assist Exception The ßoating-point assist exception is not generated by the MPC857T. Attempting to execute a ßoating-point causes an instruction implementation-speciÞc software emulation exception. 6.1.3 Implementation-Speciﬁc Exceptions The following sections describe the MPC857TÕs implementation-speciÞc exceptions. 6.1.3.1 Software Emulation Exception (0x01000) An software emulation exception occurs as a result of one of the following conditions: ¥...
Page 179 Exceptions Table 6-13. Register Settings after an Instruction TLB Miss Exception Register Setting SRR0 Set to the EA of the instruction that caused the exception. SRR1 0–30 10 1 11–150 OthersLoaded from MSR[16-31]. SRR1[30] is cleared only by loading a zero from MSR[RI]. IP No change MENo change LECopied from the ILE setting of the interrupted process...
Page 180 Exceptions The following registers are set: Table 6-15. Register Settings after an Instruction TLB Error Exception Registe Setting SRR0 Set to the EA of the instruction that caused the exception. SRR1 Note that only one of bits 1, 3, and 4 will be set. 1 1 if the translation of an attempted access is not in the translation tables.
Page 181 Exceptions Table 6-16. Register Settings after a Data TLB Error Exception (Continued) Register Setting DSISR 1 Set if the translation of an attempted access is not found in the translation tables. Otherwise, cleared 2–30 4 Set if the memory access is not permitted by the protection mechanism; otherwise cleared 6 1 for a store operation;...
Page 182 Exceptions Execution resumes from the following offsets from the base indicated by the MSR[IP]: ¥ 0x01D00ÐFor an instruction breakpoint match ¥ 0x01C00ÐFor a data breakpoint match ¥ 0x01E00ÐFor a development port maskable request or a peripheral breakpoint ¥ 0x01F00ÐFor a development port nonmaskable request 6.1.4 Implementing the Precise Exception Model Because instructions execute in parallel they may execute out of order.
Page 183 Exceptions 6.1.5 Recoverability after an Exception The processor cannot always recover from system reset and machine check interrupts, either because the conditions that cause the interrupt are catastrophic or because they caused the save/restore information in SRR0 and SRR1to be overwritten. All other PowerPC exceptions should be restartable.
Page 184 Exceptions 6.1.6 Exception Latency Figure 6-1 describes signiÞcant events during exception processing. ¥¥¥ Stage Fetch (in IQ) In dispatch entry (IQ0) Execute Complete (In CQ) In retirement entry (CQ0) Instruction Queue Completion Queue Figure 6-1. Exception Latency 6-18 MPC857T PowerQUICC User’s Manual...
Page 185 Exceptions Table 6-19. Exception Latency Kill Time Point Fetch Issue Instruction Complete Pipeline Faulting instruction issue Instruction complete and all previous instructions complete Start fetch handler Kill pipeline D (at least 3 clocks after B) First instruction of handler dispatched A At time point A the excepting instruction dispatches and begins executing.
Page 186 Exceptions 6.1.7 Partially Completed Instructions Partially completed instructions can be reexecuted after the exception is handled. This precise exception model can simplify exception processing because software does not have to save the machineÕs internal states, unwind the pipelines, or cleanly terminate the faulting instruction stream and reverse the process to resume execution of the faulting stream.
Page 187 Chapter 7 Instruction and Data Caches The MPC857T contains separate 4-Kbyte, two-way set associative instruction and data caches to allow rapid core access to instructions and data. This chapter describes the organization of the on-chip instruction and data caches, cache control, various cache operations, and the interaction between the caches, the load/store unit (LSU), the instruction sequencer, and the system interface unit (SIU).
Page 188 Instruction Cache Organization latency. Both caches provide storage for cache tags and perform cache block replacement (LRU) function. Both caches are tightly coupled to the MPC857TÕs system interface unit (SIU) to allow efÞcient access to the system memory controller and other bus masters. The SIU receives requests for bus operations from the instruction and data caches, and executes the operations per the external bus protocol.
Page 189 Instruction Cache Organization Instruction effective address Word select way0 way1 set0 tag0 w0 w1 w2 w3 tag0 w0 w1 w2 w3 set1 tag1 w0 w1 w2 w3 tag1 w0 w1 w2 w3 set126 tag126 w0 w1 w2 w3 tag126 w0 w1 w2 w3 set127 tag127 w0 w1 w2 w3...
Page 190 Instruction Cache Organization The instruction cache implements a single state bit for each cache block that indicates whether the cache block is valid or invalid. The MPC857T does not support snooping of the instruction cache. All memory is considered to have memory-coherency-not-required attributes.
Page 191 Data Cache Organization 7.2 Data Cache Organization The data cache is organized as 128 sets of two blocks as shown in Figure 7-2. Each block consists of 16 bytes, two state bits, a lock bit, and an address tag. Data effective address Byte select way0 way1...
Page 192 Cache Control Registers provide the index to select a cache set. Bits A[28Ð31] select a byte within a block. The tags consist of the high-order physical address bits PA[0Ð20]. Address translation occurs in parallel with set selection (from A[21Ð27]). The two state bits implement a three-state (modiÞed-valid/unmodiÞed-valid/invalid) protocol.
Page 193 Cache Control Registers CCER CCER FIELD — — — RESET — — — — — — — FIELD — RESET — — Figure 7-3. Instruction Cache Control and Status Register (IC_CST) Table 7-1. describes the bits of the IC_CST register. Table 7-1.
Page 194 Cache Control Registers The IC_ADR register, shown in Figure 7-4, has an SPR encoding of 561. 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 FIELD RESET —...
Page 195 Cache Control Registers Table 7-4. IC_ADR Fields for Cache Read Commands 0–17 21–27 28–29 30–31 Reserved 0 Tag 0 Way 0 Reserved Set select Word select Reserved 1 Data 1 Way 1 (0–127) (used only for data array) Chapter 7. Instruction and Data Caches...
Page 196 Cache Control Registers To read the data or tags stored in the instruction cache, do the following: 1. Write the address of the data or tag to be read to the IC_ADR according to the format shown in Table 7-6 Note that it is also possible to read this register for debugging purposes.
Page 197 Cache Control Registers 7.3.1.2.2 Instruction Cache Load & Lock Cache Block Command The instruction cache load & lock cache block command (IC_CST[CMD] = 0b011) is used to lock critical code segments in the instruction cache. Locked cache blocks are not replaced during misses and are not affected by invalidate commands.
Page 198 Cache Control Registers To load & lock one or more cache blocks: 1. Read the IC_CST error type bits to clear them. 2. Write the address of the cache block to be locked to the IC_ADR register. 3. Write the load & lock cache block command (IC_CST[CMD] = 0b011) to the IC_CST register.
Page 199 Cache Control Registers 7.3.1.2.4 Instruction Cache Unlock All Command The unlock all command (IC_CST[CMD] = 0b101) is used to unlock the entire instruction cache with a single command. When the unlock all command is performed, if a cache block is locked, it is unlocked and thereafter operates as a regular valid cache block.
Page 200 Cache Control Registers The DC_CST register, shown in Figure 7-6, has an SPR encoding of 568. CCER CCER FIELD DFWT — — — RESET — — — — — — — FIELD — RESET — — Figure 7-6. Data Cache Control and Status Register (DC_CST) Table 7-6 describes the bits of the DC_CST register.
Page 201 Cache Control Registers Table 7-6. Data Cache Control and Status Register—DC_CST (Continued) Bits Name Description 4–7 Data cache command 0000 Reserved 0001 Set forced write-through bit 0010 Cache enable 0011 Clear forced write-through bit 0100 Cache disable 0101 Set true little-endian swap bit 0110 Load &...
Page 202 Cache Control Registers Table 7-7 describes the bits of the DC_ADR register. Table 7-7. Data Cache Address Register—DC_ADR Bits Name Description 0–31 Data cache command address. When programming the DC_CST load & lock cache block, unlock cache block, and ﬂush cache block commands, DC_ADR contains the physical address of the desired cache block element in external memory.
Page 203 Cache Control Registers 1. Write the address of the copyback buffer or tag to be read to the DC_ADR according to the format shown in Table 7-9.. Note that it is also possible to read this register for debugging purposes. 2.
Page 204 Cache Control Registers Note that the data cache is disabled at hard reset. Also, the data cache is automatically disabled when a type 1 data cache error (see Table 7-6 for DC_CST[CCER1] conditions) generates a machine check exception. 7.3.2.2.2 Data Cache Load & Lock Cache Block Command The data cache load &...
Page 205 Cache Control Registers To load & lock one or more cache blocks: 1. Read the DC_CST error type bits to clear them. 2. Write the address of the cache block to be locked to the DC_ADR register. 3. Write the load & lock cache block command (DC_CST[CMD] = 0b0110) to the DC_CST register.
Page 206 PowerPC Cache Control Instructions 7.3.2.2.5 Data Cache Invalidate All Command The data cache invalidate all command (DC_CST[CMD] = 0b1100) causes all unlocked, valid blocks in the data cache to be marked invalid, regardless of whether the data is modiÞed. Therefore, this command may effectively destroy modiÞed data. To invalidate the entire data cache the invalidate all command should be preceded by an unlock all command.
Page 207 PowerPC Cache Control Instructions A TLB miss exception is generated if the effective address of one of these instructions cannot be translated and data address relocation is enabled. A TLB error exception is generated if these instructions encounter a TLB protection violation. 7.4.1 Instruction Cache Block Invalidate (icbi) The effective address is computed, translated, and checked for protection violations as deÞned in the PowerPC architecture.
Page 208 PowerPC Cache Control Instructions cache is disabled, an alignment exception is generated. If the page containing the byte addressed by the EA is caching-inhibited or write-through, then the system alignment exception handler is invoked. 7.4.4 Data Cache Block Store (dcbst) The effective address is computed, translated, and checked for protection violations as deÞned in the PowerPC architecture.
Page 209 Instruction Cache Operations 7.4.6 Data Cache Block Invalidate (dcbi) The effective address is computed, translated, and checked for protection violations as deÞned in the PowerPC architecture. This instruction is treated as a store with respect to address translation and memory protection. If the address hits in the cache, the cache block is placed in the invalid state, regardless of whether the data is modiÞed.
Page 210 Instruction Cache Operations The data path for the instruction cache and its surrounding logic are shown in Figure 7-9. Address [21–27] Instruction Cache Decoder Array Address [28–29] 4-Word Cache Block Buffer Stream Word 4-Word Select Burst Buffer 2->1 4->1 Data Bypass 2->1 To Instruction...
Page 211 Instruction Cache Operations The MPC857T instruction cache includes the following operational features: ¥ Instruction fetch latency is reduced by sending the requested instruction address to the instruction cache and internal bus simultaneously. A cache hit aborts the internal bus transaction before the MPC857T can initiate an external fetch. ¥...
Page 212 Instruction Cache Operations The instruction cache is not blocked to internal accesses while the fetch (caused by a cache miss) completes. This functionality is sometimes referred to as Ôhits under misses,Õ because the cache can service a hit while a cache miss Þll is waiting to complete. If no bus errors are encountered during the 4-word cache block fetch, the burst buffer is marked valid and written to the cache array, provided the cache array is not busy servicing a hit.
Page 213 Data Cache Operation 7.5.5 Updating Code and Memory Region Attributes The instruction cache does not perform snooping, so if a processor modiÞes a memory location that may be contained in the instruction cache, software must ensure that such memory updates are visible to the instruction fetching mechanism. Also, whenever the memory/cache attributes of any memory region are changed, it is critical that the cache contents reßect the new attributes.
Page 214 Data Cache Operation The MPC857T data cache includes the following operational features: ¥ Single-cycle cache access on hit and one clock latency added for miss ¥ The data cache supports hits under load misses ¥ 1-word store buffer ¥ Store misses bypass the data cache (no-allocate store miss) in write-through mode ¥...
Page 215 Data Cache Operation If a bus error is encountered while loading the requested data (the critical word), then a machine check exception is generated. If a bus error occurs while loading subsequent words in the cache block, then the cache block is marked invalid. After the cache block with the requested data has been loaded from memory, the modiÞed-valid cache block in the copyback buffer is sent to the SIU to be written to memory.
Page 216 Data Cache Operation 7.6.4.2 Data Cache Store Miss in Write-Back Mode In the case of a data cache store miss in write-back mode, the data cache must establish the block in the cache array before modifying that block. Therefore, a block in the cache array is selected to receive the data from memory and from the load/store unit.
Page 217 Data Cache Operation caching-inhibited regions have not been previously loaded into the data cache, or, if they have, that those blocks have been ßushed from the cache. Whenever the memory/cache attributes of any memory region are changed (for example, from caching-allowed to caching-inhibited), it is critical that the cache contents reßect the new attributes.
Page 218 Cache Initialization after Reset If a memory region is marked caching-allowed, the MPC857T assumes that it is the single master in the system to that region. If a caching-allowed lwarx or stwcx. access misses in the data cache, the transaction on the internal and external buses do not have a reservation. If the memory region is marked caching-inhibited or the cache is locked, and the access misses, then the lwarx instruction appears on the bus as a single-beat load with the reservation.
Page 219 Debug Support 7.8.1 Instruction and Data Cache Operation in Debug Mode The development system interface of the MPC857T uses the development port, which is a dedicated serial port. The development port is a relatively inexpensive interface that allows a development system to operate in a lower frequency than the coreÕs frequency and controls system activity when the core is in debug mode.
Page 220 Debug Support 3. Use the load & lock cache block command to restore the old sets in the cache array 4. Unlock any ways of the original sets that were not previously locked 5. To restore the old state of the LRU bits make sure that the last access (load & lock cache block or unlock cache block command) is performed on the most-recently used way (not the LRU way).
Page 221 Chapter 8 Memory Management Unit The MPC857T implements a virtual memory management scheme that provides cache control, memory access protections, and effective-to-physical (real) address translation. The MMU largely complies with the PowerPC operating environment architecture (OEA) with respect to architecturally deÞned memory management features that are appropriate for this implementation.
Page 222 PowerPC Architecture Compliance ¥ Supports 16 access protection groups (group protection overrides page protection) ¥ Separate -entry, fully-associative data translation lookaside buffer (DTLB) and instruction TLB (ITLB) with the following features: Ñ Implementation-speciÞc exceptionsÑITLB and DTLB miss exceptions, ITLB and DTLB error exceptions Ñ...
Page 223 Address Translation 8.3 Address Translation The core generates 32-bit effective addresses (EA) for memory accesses. Setting MSR[IR] and MSR[DR] enables the effective-to-real translation for instruction fetching and data accesses, respectively. Section 8.3.1, ÒTranslation Disabled,Ó describes behavior when translation is disabled. Section 8.3.2, ÒTranslation Enabled,Ó describes behavior when translation is enabled.
Page 224 Address Translation A TLB hit in multiple entries is avoided when a TLB is being reloaded. When TLB logic detects that a new effective page number (EPN) overlaps one in the TLB (when taking into account pages sizes, subpage validity ßags, user/supervisor state, address pace ID (ASID), and the SH values of the TLB entries), the new EPN is written and the old one is invalidated.
Page 225 Address Translation Data/Instruction Fetch 32-bit EA is generated Compare address with TLB (0 clock penalty) entries Is page TLB error exception valid TLB reload (read page Access permitted description from external by page protection memory to TLB) (20–23 clock penalty @ one wait-state external memory) Use page description from TLB...
Page 226 Using Access Protection Groups MSR[PR] M_CASID[CASID] 32-Bit EA 20-Bit 32-Bit Logical Page Byte Address 20-Bit 12-Bit Implementation- Specific TLB Miss Exceptions Page Protection 32-Entry Fully Associative TLB to Core Free Access 20-Bit Protection Implementation- Group Number Physical Page Number Byte Specific Error Exceptions No Access...
Page 227 Protection Resolution Modes 8.5 Protection Resolution Modes The MMUs can be programmed in three different modes that have different methods of deÞning the protection resolution of the address space. These are as follows: ¥ Mode 1ÑProtection resolution to 4-Kbyte minimum page size. This is the simplest mode with the most efÞcient memory size (that is, MMU tables are smaller).
Page 228 Memory Attributes In this mode, the MMU page tables deÞned for the software tablewalk resolve to a single level-two descriptor entry for a 1-Kbyte page. This is done by allowing manipulation of the subpage validity ßags of a 4-Kbyte page. For example: Ñ...
Page 229 Translation Table Structure The G attribute is used to map I/O devices that are sensitive to speculative (out-of-order) accesses. An attempted speculative access to a page marked guarded (G = 1) stalls until either the access is nonspeculative or is canceled by the core. Attempting to fetch from guarded memory causes an implementation-speciÞc instruction TLB error interrupt.
Page 230 Translation Table Structure When MD_CTR[TWAM] = 1, the tablewalk begins at the level-one base address in M_TWB. EA[0Ð9] indicates the level-one page descriptor. As shown in Table 8-1, an 8-Mbyte page requires two identical entries in the level-one table, one for bit 9 = 0 and one for bit 9 = 1.
Page 231 Translation Table Structure Effective Address Level-1 Table Pointer (M_TWB) Level-1 Index Level-2 Index Page Offset 18-Bit 12-Bit Level-1 Table Base Level-1 Index Level-1 Table 18-Bit 12-Bit Level-1 Descriptor 0 12 for 1 Kbyte 12 for 4 Kbyte Level-1 Descriptor 1 14 for 16 Kbyte 10-Bit 19 for 512 Kbyte...
Page 232 Translation Table Structure Table 8-2. Number of Replaced EA Bits per Page Size (Continued) Page Size Number of Replaced EA Bits 512 Kbyte 8 Mbyte The page size and the level-two base address are read from the level-one descriptor. If the page size is 512 Kbytes or 8Mbytes, the level-two base address is used directly as the address of the level-two descriptor.
Page 233 Translation Table Structure 8.7.2 Level-Two Descriptor Table 8-4 describes the level-two descriptor format supported by hardware. (Section 8.5, ÒProtection Resolution Modes,Ó describes the protection modes.) Table 8-4. Level-Two (Page) Descriptor Format Bits Name Mode 2 Mode 1 or Mode 3 0–19 Physical (real) page number 20–21 PP...
Page 234 Programming Model 8.7.3 Page Size The page size is determined by a combination of two Þelds: the page-size (PS) Þeld in the level-one descriptor and the small-page-size (SPS) Þeld in the level-two descriptor. Table 8-5 shows how the two Þelds select the page size. Table 8-5.
Page 235 Programming Model Table 8-6. MPC857T-Specific MMU SPRs (Continued) Register Name Section M_TWB MMU tablewalk base register 8.8.8 Protection Registers M_CASID CASID register 8.8.9 MI_AP IMMU access protection register 8.8.10 MD_AP DMMU access protection register Scratch Register M_TW MMU tablewalk special register 8.8.11 Debug Registers MI_CAM...
Page 236 Programming Model Table 8-7 describes MI_CTR Þelds. Table 8-7. MI_CTR Field Descriptions Bits Name Description Group protection mode 0 PowerPC mode 1 Domain manager mode Page protection mode. Valid regardless of whether translation is enabled. If translation is enabled, PPM determines how Mx_RPN is interpreted. See Table 8-12 and Table 8-13. 0 Page resolution of protection 1 1-Kbyte resolution of protection for 4-Kbyte pages CIDEF...
Page 237 Programming Model Table 8-8 describes MD_CTR Þelds. Table 8-8. MD_CTR Field Descriptions Bits Name Description Group protection mode 0 PowerPC mode 1 Domain manager mode Page protection mode 0 Page resolution of protection 1 1-Kbyte resolution of protection for 4-Kbyte pages CIDEF CI default when the DMMU is disabled (MSR[DR] = 0) 0 Caching is allowed.
Page 238 Programming Model Table 8-9 describes Mx_EPN Þelds. Table 8-9. M x _EPN Field Descriptions Bits Description 0–19 Effective page number for TLB entry. Default value is the EA of the last ITLB/DTLB miss 20–21 — Reserved. Ignored on write. Undeﬁned on read TLB entry valid bit.
Page 239 Programming Model Table 8-10. MI_TWC Field Descriptions (Continued) Bits Name Description — Reserved. Ignored on write. Returns 0 on read. Entry valid bit 0 Entry is not valid 1 Entry is valid. Default value on ITLB miss. 8.8.5 DMMU Tablewalk Control Register (MD_TWC) The DMMU tablewalk control register (MD_TWC), shown in Figure 8-10, contains the level-two pointer and access protection group of an entry to be loaded into the TLB.
Page 240 Programming Model Table 8-11. MD_TWC Field Descriptions (Continued) (Continued) Name Description Bits Write Read Write Read — Writethrough attribute for page entry: Returns 0 on read. 0 Copyback data cache policy. Cleared on DTLB miss. 1 Writethrough data cache policy —...
Page 241 Programming Model Table 8-12 describes MI_RPN Þelds. (Section 8.5, ÒProtection Resolution Modes,Ó describes the protection modes.) Table 8-12. MI_RPN Field Descriptions Bits Name Mode 2 Mode 1 or Mode 3 0–19 Real (physical) page number 20–21 Protection attributes for Extended Encoding: PowerPC Encoding: subpages 1–4.
Page 242 Programming Model Field Reset — Field Reset — Figure 8-12. DMMU Real Page Number Register (MD_RPN) Table 8-13 describes MD_RPN Þelds. (Section 8.5, ÒProtection Resolution Modes,Ó describes the protection modes.) Table 8-13. MD_RPN Field Descriptions Bits Name Mode 2 Mode 1 or Mode 3 0–19 Real (physical) page number 20–21...
Page 243 Programming Model 8.8.8 MMU Tablewalk Base Register (M_TWB) The MMU tablewalk base register (M_TWB), shown in Figure 8-13, contains a pointer to the level-one table to be used in hardware-assisted tablewalk mode. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Field L1TB L1TB...
Page 244 Programming Model 8.8.10 MMU Access Protection Registers (MI_AP/MD_AP) The IMMU access protection register (MI_AP, SPR 786) contains the settings for the access protection groups for the IMMU. The DMMU access protection register (MD_AP, SPR 794) is identical. Both registers are shown in Figure 8-15. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Field GP0 GP1 GP2 GP3 GP4 GP5 GP9 GP10 GP11 GP12 GP13 GP14 GP15...
Page 245 Programming Model 8.8.12.1 IMMU CAM Entry Read Register (MI_CAM) Figure 8-17 shows the MMU instruction CAM entry read register (MI_CAM). When the content-addressable memory of the MI_CAM register is read, it contains the effective address and page sizes of an entry indexed by MI_CTR[ITLB_INDX]. MI_CAM is updated only by writing to it.
Page 246 Programming Model 8.8.12.2 IMMU RAM Entry Read Register 0 (MI_RAM0) The IMMU RAM entry read register 0 (MI_RAM0), shown in Figure 8-18, contains the physical page number and page attributes of an entry indexed by MI_CTR[ITLB_INDX]. This register is updated only when MI_CAM is updated. Field Reset —...
Page 247 Programming Model 8.8.12.3 IMMU RAM Entry Read Register 1 (MI_RAM1) The IMMU RAM entry read register 1 (MI_RAM1), shown in Figure 8-19, contains the protection mode information of the entry indexed by MI_CTR[ITLB_INDX]. This register is updated only when MI_CAM is written to. Field —...
Page 248 Programming Model Field Reset — R(/W) Field SPVF ASID Reset — R(/W) Figure 8-20. DMMU CAM Entry Read Register (MD_CAM) Table 8-20 describes MD_CAM Þelds. Table 8-20. MD_CAM Field Descriptions Bits Name Description 0–19 Effective page number SPVF Subpage validity ﬂags 0 Subpage 0 (address[20–21] = 00) is not valid 1 Subpage 0 (address[20–21] = 00) is valid 0 Subpage 1 (address[20–21] = 01) is not valid...
Page 249 Programming Model Field Reset — Field APGI — Reset — Figure 8-21. DMMU RAM Entry Read Register 0 (MD_RAM0) Table 8-21 describes MD_RAM0 Þelds. Table 8-21. MD_RAM0 Field Descriptions Bits Name Description 0–19 Real (physical) page number 20–22 PS Page size. (Values not shown are reserved) 000 4 Kbyte 001 16 Kbyte 011 512 Kbyte...
Page 250 Programming Model Field — Reset Field — SAT URP0 UWP0 URP1 UWP1 URP2 UWP2 URP3 UWP3 Reset — — — — — — — — — — — — Figure 8-22. DMMU RAM Entry Read Register 1 (MD_RAM1) Table 8-22 describes MD_RAM1 Þelds. Table 8-22.
Page 251 Memory Management Unit Exceptions Table 8-22. MD_RAM1 Field Descriptions (Continued) Bits Name Description URP2 0 Subpage 2 (address[20–21] = 10) User read access is not permitted 1 Subpage 2 (address[20–21] = 10) User read access is permitted UWP2 0 Subpage 2 (address[20–21] = 10) User write access is not permitted 1 Subpage 2 (address[20–21] = 10) User write access is permitted URP3 0 Subpage 3 (address[20–21] = 11) User read access is not permitted...
Page 252 TLB Manipulation 8.10.1 TLB Reload The TLB reload (tablewalk) function is performed in the software with some hardware assistance. It consists of the following actions: ¥ Automatic storage of the missed data or instruction EA and default attributes in MI_EPN or MD_EPN. This value is loaded into the selected entry on a write to MI_RPN or MD_RPN.
Page 253 TLB Manipulation Figure 8-24 performs an ITLB reload itlb_swtw mtspr M_TW, R1 # Save R1 mfspr R1, SRR0 # Load R1 with instruction miss EA (the same data # may be taken from MI_EPN) mtspr MD_EPN, R1 # Save instruction miss EA in MD_EPN mfspr R1, M_TWB # Load R1 with level-1 pointer R1, (R1)
Page 254 TLB Manipulation 6. Run software tablewalk code to load the appropriate entry into the translation lookaside buffer. See Section 8.10.1.1, ÒTranslation Reload Examples.Ó 7. Repeat steps 4Ð6 to load other TLB entries. 8. Set MI_CTR[RSV4I] (MD_CTR[RSV4D]). 8-34 MPC857T PowerQUICC User’s Manual...
Page 255 TLB Manipulation 8.10.4 TLB Invalidation Executing tlbie invalidates TLB entries that hit, including reserved entries. Note that EA[0Ð21] is used in the comparison because segment registers as deÞned by the PowerPC architecture are not implemented. Although for entries with pages larger than 4 Kbytes, some lower bits of the effective page number are ignored.
Page 256 TLB Manipulation 8-36 MPC857T PowerQUICC User’s Manual...
Page 257 Chapter 9 Instruction Execution Timing This chapter describes the timing of PowerPC instructions that execute in the core. Examples show stalls and bubbles due to serialization, latency, and blockage. 9.1 Instruction Execution Timing Examples The following sections provide timings for the following scenarios: ¥...
Page 258 Instruction Execution Timing Examples GCLK1 addic mulli addi Fetch Decode addic Read + Execute Bubble addic Writeback addic L Address Drive L Data Load Write Back Figure 9-1. Data Cache Load Timing 9.1.2 Writeback Arbitration In Figure 9-2, the addic instruction is dependent on the mulli result. Because the single-cycle instruction sub has priority on the writeback bus over the mulli, the mulli writeback is delayed one clock and causes a bubble in the execute stream.
Page 259 Instruction Execution Timing Examples 9.1.3 Private Writeback Bus Load In Figure 9-4, lwz and xor write back in the same clock since they use the writeback bus in two different ticks (a tick = 1/4 of a processor clock). r12,64 (SP) r5,r5,3 cror 4,14,1...
Page 260 Instruction Execution Timing Examples 9.1.5 A Full Completion Queue Figure 9-6 shows stalls due to a full CQ. Here, the CQ is full from executing sub, addic, and and. It takes one more bubble from the load writeback to allow further issue while the CQ retires sub, addic, and and.
Page 261 Instruction Execution Timing Examples GCLK1 Fetch addic Bubble mulli addi Decode addic mulli Read + Execute Bubble Bubble addic mulli Writeback addic L Address Drive L Data Load Writeback Branch Decode Branch Execute Figure 9-7. Branch Folding Timing 9.1.7 Branch Prediction In this example, the blt instruction is dependent on the cmpi instruction.
Page 262 Instruction Timing List 9.2 Instruction Timing List Table 9-1 summarizes instruction execution timings in terms of latency and blockage of the appropriate execution unit. A serializing instruction blocks all execution units. Table 9-1. Instruction Execution Timing Instructions Latency Blockage Unit Serializing Branch: b, ba, bl, bla, bc, bca, bcl, bcla, bclr, bclrl, Taken 2...
Page 263 Instruction Timing List Table 9-1. Instruction Execution Timing (Continued) Instructions Latency Blockage Unit Serializing Move to/from SPR (Debug, DAR, DSISR): mtspr, mfspr Serialize + 1 String instructions: lswi, lswx, stswi, stswx. See Serialize + 1 + no. of words Section 9.2.2, “String Instruction Latency.” accessed Memory control instructions: isync Serialize...
Page 264 Instruction Timing List 9.2.2 String Instruction Latency String accesses require separate aligned bus accesses. Figure 9-9 shows the maximum number of bus cycles needed for string accesses where the beginning and end are unaligned. 0x00 0x04 2 bus cycles 0x08 Word transfers 0x0C 3 bus cycles...
Page 265 Part III Conﬁguration and Reset Audience Part III is intended for system designers and programmers who need to understand the operation of the MPC857T at start up. It assumes an understanding of the PowerPC programming model described in the previous chapters and a high level understanding of the MPC857T.
Page 266 Italics indicate variable command parameters, for example, bcctrx. italics Book titles in text are set in italics. PreÞx to denote hexadecimal number PreÞx to denote binary number Instruction syntax used to identify a source GPR rA, rB Instruction syntax used to identify a destination GPR REG[FIELD] Abbreviations or acronyms for registers or buffer descriptors are shown in uppercase text.
Page 267 Table iv. Acronyms and Abbreviated Terms (Continued) Term Meaning Load/store unit Memory management unit Most-signiﬁcant byte Most-signiﬁcant bit Machine state register Peripheral component interconnect RISC Reduced instruction set computing RTOS Real-time operating system Receive Special-purpose register Software watchdog timer Time base register Translation lookaside buffer Transmit Part III.
Page 268 Part III-iv MPC857T PowerQUICC User’s Manual...
Page 269 Chapter 10 System Interface Unit The system interface unit (SIU) controls system startup, initialization and operation, protection, as well as the external system bus. The system conÞguration and protection function controls the overall system and provides various monitors and timers, including the bus monitor, software watchdog timer, periodic interrupt timer (PIT), PowerPCª...
Page 270 Features 10.1 Features The following is a list of the SIUÕs main features: ¥ System conÞguration and protection ¥ System interrupt conÞguration ¥ System reset monitoring and generation ¥ Clock synthesizer ¥ Power management ¥ Real-time clock ¥ PowerPC decrementer ¥...
Page 271 System Conﬁguration and Protection ¥ PowerPC timebase counterÑProvides a timebase reference for the operating system or application software. This 64-bit timebase counter is deÞned by the PowerPC architecture and has two independent reference registers that generate a maskable interrupt when the programmed value in one of the registers is reached. The associated bit in the timebase status and control register (TBSCR) is set for the reference register that generated the interrupt.
Page 272 Multiplexing SIU Pins 10.3 Multiplexing SIU Pins Due to the limited number of pins available in the MPC857T package, some of the functionalities share pins. Table 10-1 shows how the functionality is controlled on each pin. Table 10-1. Multiplexing Control Name Pin Conﬁguration Control TSIZ0/REG...
Page 273 Programming the SIU 10.4 Programming the SIU The following sections describe registers used for programming the SIU. 10.4.1 Internal Memory Map Register (IMMR) The internal memory map register (IMMR) is an SPR that identiÞes speciÞc devices and the internal memory map base address. Using mfspr, software can read IMMR to determine the location and availability of any on-chip system resource.
Page 274 Programming the SIU 10.4.2 SIU Module Conﬁguration Register (SIUMCR) The SIU module conÞguration register (SIUMCR) contains bits that conÞgure the following features in the SIU: ¥ External bus arbitration ¥ External master support ¥ Debug and test port conÞguration ¥ System interface pin conÞguration ¥...
Page 275 Programming the SIU Table 10-3. SIUMCR Field Descriptions (Continued) Bits Name Description 11–12 DBPC Debug port pins conﬁguration. Determines the active pins for the development port. The default is set by the hard reset conﬁguration word. See Section 11.3.1.1, “Hard Reset Conﬁguration Word” for the description of these bits.
Page 276 Programming the SIU Field SWTC Reset 1111_1111_1111_1111 (IMMR & 0xFFFF0000) + 0x004 Field — SWF SWE SWRI SWP Reset 1111_1111 (IMMR & 0xFFFF0000) + 0x006 Figure 10-4. System Protection Control Register (SYPCR) Table 10-4 describes SYPCR Þelds. Table 10-4. SYPCR Field Descriptions Bits Name Description...
Page 277 Programming the SIU 10.4.4 Transfer Error Status Register (TESR) The transfer error status register (TESR) has a bit for each transfer error exception source. Set bits indicate what type of transfer error exception that occurred since bits were last cleared. Bits are cleared by reset or by writing ones to them. Canceled speculative accesses that do not cause an interrupt may set these bits.
Page 278 Programming the SIU 10.4.5 Register Lock Mechanism If the MPC857T sets PLPRCR[LPM] = 11 before entering power-down mode, then the registers of the SIU maintained by KAPWR are automatically protected. However, to provide protection of the SIU registers maintained by KAPWR against uncontrolled shutdown, a register locking mechanism is included.
Page 279 System Conﬁguration When a register is locked, an attempt to write to it will result in a machine check exception, and will not change the value in the register. One exception to this is the timebase register (TBU and TBL), locked with TBK. A write to the timebase register when it is locked results in a software emulation exception.
Page 280 System Conﬁguration Software Watchdog Timer Generator IRQ[0:7] IRQ0 Edge Detector Decrementer Decrementer Selector Level 7 Timebase Level 6 PowerPC CORE Periodic Level 5 Interrupt Timer Level 4 Real-Time Clock Interrupt External Controller Level 3 Interrupt PCMCIA Level 2 Level 1 Level 0 Debug Debug...
Page 281 System Conﬁguration 10.5.2 Priority of Interrupt Sources There are eight external IRQ pins (IRQ0 is essentially nonmaskable, although in a limited sense it can be masked as shown in Table 10-8) and eight interrupt levels. Asserting IRQ0 causes an NMI. The other 15 interrupt sources assert a single interrupt request to the core (the external interrupt).
Page 282 System Conﬁguration 10.5.3 SIU Interrupt Processing Figure 10-8 shows the general ßow of SIU interrupt processing. Start SIU interrupt occurs Set bit in SIPEND Bit set in SIMASK Bit not set in SIMASK Assert external interrupt to core Figure 10-8. SIU Interrupt Processing 10.5.3.1 Nonmaskable Interrupts—IRQ0 and SWT Figure 10-9 is a logical representation of IRQ0.
Page 283 System Conﬁguration Table 10-8. IRQ0 Versus IRQ x Operation IRQ x Functionality IRQ0 Exception Vector 0x100 0x500 Core input External interrupt SIMASK Not used, except for enabling SIVEC Used for masking SIVEC Not normally used. If used, SIMASK[IRQ0] Supplies the interrupt code so the core knows must be set.
Page 284 System Conﬁguration Table 10-9 describes SIPEND Þelds. Table 10-9. SIPEND Field Descriptions Bits Description 0, 2, 4, IRQn Interrupt request 0–7. Indicate whether an edge-triggered interrupt is pending. 6, 8, 0 The appropriate interrupt is not pending. 1 The appropriate interrupt is pending. 10, 12, 1, 3, 5, LVLn...
Page 285 System Conﬁguration 10.5.4.2 SIU Interrupt Mask Register (SIMASK) Bits in SIMASK correspond to the interrupt request bits in SIPEND. Setting SIMASK bits enable the generation of interrupt requests to the core. SIMASK is updated by the software, which must determine which interrupt sources are enabled at a given time. Field IRM0 LVM0 IRM1 LVM IRM2 LVM2 IRM3 LVM3 IRM4 LVM4 IRM5 LVM5 IRM6 LVM6 IRM7 LVM7...
Page 286 System Conﬁguration 10.5.4.3 SIU Interrupt Edge/Level Register (SIEL) Bits in SIEL, shown in Figure 10-12, deÞne interrupts as edge- or level-triggered and enable/disable their use as wake-up signals in low-power mode. Field ED0 WM0 ED1 WM1 ED2 WM2 ED3 WM3 ED4 WM4 ED5 WM5 ED6 WM6 ED7 WM7 Reset 0000_0000_0000_0000 Addr...
Page 287 System Conﬁguration 10.5.4.4 SIU Interrupt Vector Register (SIVEC) The SIU interrupt vector register (SIVEC) is shown in Figure 10-13 Field INTC — Reset 0011_1100_0000_0000 Addr (IMMR & 0xFFFF0000) + 0x01C Field — Reset 0000_0000_0000_0000 Addr (IMMR & 0xFFFF0000) + 0x01E Figure 10-13.
Page 288 The Bus Monitor Intr: • • • Intr: • • • Save State Save State R3 < – @ SIVEC R3 < – @ SIVEC R4 < – Base of Branch Table R4 < – Base of Branch Table • • • •...
Page 289 The Software Watchdog Timer the bus monitor terminates the cycle by internally asserting TEA. The programmability of the timeout allows for a variation in system peripheral response time. The timing mechanism is clocked by the system clock divided by eight. The maximum value is 2,040 system clocks.
Page 290 The Software Watchdog Timer software watchdog expiration request is issued to the reset or NMI control logic. At reset, the value in SWTC is set to the maximum value and is loaded into the software watchdog down-counter, starting the process. Although most software disciplines permit or encourage the watchdog concept, some systems require a selection of timeout periods.
Page 291 The PowerPC Decrementer Table 10-13. describes SWSR Þelds. Table 10-13. SWSR Field Descriptions Bits Name Description 0–15 Sequence. This ﬁeld is the pattern that is used to control the state of the software watchdog timer. 10.8 The PowerPC Decrementer A PowerPC-deÞned 32-bit decrementing counter supports the decrementer interrupt. In the MPC857T, the decrementer is clocked by TMBCLK, so TBSCR[TBE] must be set for the decrementer to start.
Page 292 The PowerPC Timebase 10.8.1 Decrementer Register (DEC) The decrementer register (DEC) is a PowerPC SPR. It can be read or written to by mfspr or mtspr. DEC is powered by KAPWR and continues counting when KAPWR is applied. Control of the decrementer is provided in the TBSCR. The decrementer and timebase use TMBCLK.
Page 293 The PowerPC Timebase 10.9.1 Timebase Register (TBU and TBL) The timebase register (TB) holds a 64-bit integer that is incremented periodically. It is implemented in two parts, time base upper and time base lower (TBU and TBL). There is no automatic initialization of TB, therefore, system software must perform this initialization.
Page 294 The PowerPC Timebase 10.9.2 Timebase Reference Registers (TBREFA and TBREFB) TBREFA and TBREFB are associated with TBL. When the contents of TBL matches a reference register, a reference event is signaled in TBSCR[REFA] or TBSCR[REFB]. These events can generate interrupts, if enabled. Note that TBREFA and TBREFB are keyed registers.
Page 295 The Real-Time Clock Table 10-19 describes TBSCR Þelds. Table 10-19. TBSCR Field Descriptions Bits Name Description 0–7 TBIRQ Timebase interrupt request. Determines interrupt priority level of the timebase. To specify a certain level, the appropriate bit should be set. REFA Reference interrupt status.
Page 296 The Real-Time Clock RTSEC Interrupt Clock Divide PITRTCLK 32-Bit Counter Disable by 8,192 Clock Alarm Divide by 9,600 Interrupt 32-Bit Register Figure 10-23. Real-Time Clock Block Diagram 10.10.1 Real-Time Clock Status and Control Register (RTCSC) The real-time clock status and control register (RTCSC) is used to enable the different real-time clock functions and for reporting interrupt sources.
Page 297 The Real-Time Clock Table 10-20. RTCSC Field Descriptions (Continued) Bits Name Description Real-time clock freeze enable 0 The real-time clock is unaffected by the FRZ signal. 1 The FRZ signal stops the real-time clock. Real-time clock enable. If set, real-time clock timers are enabled. 10.10.2 Real-Time Clock Register (RTC) The 32-bit real-time clock register (RTC) contains the current value of the real-time clock.
Page 298 The Real-Time Clock Field ALARM Reset — Addr (IMMR & 0xFFFF0000) + 0x22C Field ALARM Reset — Addr (IMMR & 0xFFFF0000) + 0x22E Figure 10-26. Real-Time Clock Alarm Register (RTCAL) Table 10-22 describes RTCAL Þelds. Table 10-22. RTCAL Field Descriptions Bits Name Description...
Page 299 The Periodic Interrupt Timer (PIT) Table 10-23 describes RTSEC Þelds. Table 10-23. RTSEC Field Descriptions Bits Name Description 0–13 COUNTER Counter bits (fraction of a second). Bit 13 is always the lsb of the count. It either resets at 8192 or at 9600, as programmed.
Page 300 The Periodic Interrupt Timer (PIT) The time-out period is calculated as follows: PITC 1 PITC 1 ------------------------ - ----------------------------------------------------------- - period æ ExternalClock ö ¸ pitrtclk ----------------------------------------- - è ø Solving this equation using a 32.768-KHz external clock gives: PITC 1 PITperiod ------------------------ - 8192...
Page 301 The Periodic Interrupt Timer (PIT) Table 10-24. PISCR Field Descriptions (Continued) Bits Name Description PITF PIT freeze enable 0 The PIT is unaffected by the FRZ signal. 1 The FRZ signal stops the PIT. Periodic timer enable 0 The PIT is disabled. 1 The PIT is enabled.
Page 302 General SIU Timers Operation 10.11.3 PIT Register (PITR) The PIT register (PITR) is a read-only register that shows the current value in the periodic interrupt down counter. Writes to PITR do not affect it; reads do not affect the counter. Field Reset —...
Page 303 General SIU Timers Operation 10.12.2 Low-Power Stop Operation When the PowerPC core is set in a low-power mode (doze, sleep, deep sleep), the software watchdog timer is frozen. It remains frozen and maintains its count value until the core exits this mode and continues to execute instructions.
Page 304 General SIU Timers Operation 10-36 MPC857T PowerQUICC User’s Manual...
Page 305 Chapter 11 Reset The reset block has reset control logic that determines the cause of reset, synchronizes it if necessary, and resets the appropriate logic modules. The memory controller, system protection logic, interrupt controller, and parallel I/O signals are initialized only on hard reset.
Page 306 Types of Reset ¥ JTAG reset ¥ External soft reset ¥ Internal soft reset Ñ Debug port soft reset All of these reset sources are fed into the reset controller and, depending on the source of the reset, different actions are taken. The reset status register reßects the last source to cause a reset.
Page 307 Types of Reset established, and the core stops driving the HRESET and SRESET signals. Following the negation of HRESET and SRESET a 16-cycle period passes before an external hard or soft reset will be sampled. Note that external pull-up resistors should be provided to drive HRESET and SRESET high.
Page 308 Types of Reset 11.1.6 Power-On and Hard Reset Sequence Figure 11-1 shows the reset sequence following a power-on or internal or external hard reset event. • Power-On Sample MODCK pins and initialize clocks Power On • Reset HRESET and SRESET are asserted PORESET is Negated and PLL Lock Internally •...
Page 309 Reset Status Register (RSR) 11.1.9 Soft Reset Sequence Figure 11-2 shows the reset sequence following an internal or external soft reset event. • SRESET assert Internal or external Internal initiated • SRESET asserted SRESET The time counter is set to 512 Timer expires (after 512 clocks) •...
Page 310 MPC857T Reset Conﬁguration Table 11-2. Reset Status Register Bit Settings Bits Name Description EHRS External hard reset status. Set by a power-on reset. When an external hard reset event is detected, EHRS is set and remains set until software clears it. 0 No external hard reset event occurred.
Page 311 MPC857T Reset Conﬁguration 11.3.1 Hard Reset When a hard reset event occurs, the MPC857T determines its initial mode of operation by sampling the values present on the data bus (D[0Ð31]) or from an internal default constant (D[0Ð31] = 0x00000000). If the RSTCONF signal is asserted at sampling time, the conÞguration is sampled from the data bus.
Page 312 MPC857T Reset Conﬁguration CLKOUT PORESET INTPORESET HRESET RSTCONF TSUP D[0:31] Default RSTCONF Controlled Figure 11-5. Reset Configuration Sampling for Short PORESET Assertion Figure 11-6 shows a reset operation with a long PORESET signal assertion. CLKOUT PORESET INTPORESET HRESET RSTCONF TSUP D[0:31] Default RSTCONF Controlled...
Page 313 MPC857T Reset Conﬁguration Figure 11-7 shows the conÞguration data sampling timing relative to HRESET and CLKOUT. CLKOUT HRESET Maximum Time of Reset Recognition RSTCONF Data Reset Configuration Word Maximum Setup Time of Reset Recognition Sample Data Sample Data Sample Data Configuration Configuration Configuration...
Page 314 MPC857T Reset Conﬁguration Table 11-3. Hard Reset Configuration Word Field Descriptions (Continued) Bits Name Description BDIS Boot disable. If BDIS is set, memory bank 0 is invalid; that is, BR0[V] is cleared. (See Section 15.4.1, “Base Registers (BRx).”) 0 The memory controller is activated after reset so that it matches all addresses. 1 The memory controller is cleared after reset but is not activated.
Page 315 TRST and Power Mode Considerations Table 11-3. Hard Reset Configuration Word Field Descriptions (Continued) Bits Name Description 13– EBDF External bus division factor. Deﬁnes the frequency division factor between GCLK1/GCLK2 and GCLK1_50/GCLK2_50. CLKOUT is similar to GCLK2_50. GCLK2_50 and GCLK1_50 are used by the system interface unit and memory controller to interface with the external system.
Page 316 TRST and Power Mode Considerations 11-12 MPC857T PowerQUICC User’s Manual...
Page 317 Part IV The Hardware Interface Intended Audience Part IV is intended for system designers who need to understand how each MPC857T signal works and how those signals interact. Contents Part IV describes external signals, clocking, memory control, and power management of the MPC857T.
Page 318 Suggested Reading This section lists additional reading that provides background for the information in this manual as well as general information about the PowerPC architecture. MPC8xx Documentation Supporting documentation for the MPC857T can be accessed through the world-wide web at http://www.motorola.com/SPS/RISC/netcomm. This documentation includes technical speciÞcations, reference materials, and detailed applications notes.
Page 319 Indicates an undeÞned numerical value NOT logical operator ¬ & AND logical operator OR logical operator Acronyms and Abbreviations Table i contains acronyms and abbreviations used in this document. Note that the meanings for some acronyms (such as SDR1 and DSISR) are historical, and the words for which an acronym stands may not be intuitively obvious.
Page 320 Table v. Acronyms and Abbreviated Terms (Continued) Term Meaning Least recently used Least-signiﬁcant byte Least-signiﬁcant bit Load/store unit Multiply accumulate Memory management unit Most-signiﬁcant byte Most-signiﬁcant bit Machine state register NMSI Nonmultiplexed serial interface Open systems interconnection Peripheral component interconnect PCMCIA Personal Computer Memory Card International Association Primary rate interface...
Page 321 Table v. Acronyms and Abbreviated Terms (Continued) Term Meaning User-programmable machine USART Universal synchronous/asynchronous receiver/transmitter Part IV. The Hardware Interface Part IV-v...
Page 322 Part IV-vi MPC857T PowerQUICC User’s Manual...
Page 323 Chapter 12 External Signals This chapter contains descriptions of the MPC857T input and output signals, showing multiplexing, pin assignments, and reset values. Figure 12-1 shows the signals grouped by function. Chapter 12. External Signals 12-1...
Page 324 V DDSYN /V SSSYN /V SSSYN1 / V DDH /V DDL /V SS /KAPWR A[0–31] RxD1/PA15 TSIZ0/REG TxD1/PA14 TSIZ1 PA13 PA12 BURST PA11 BDIP/GPL_B5 PA10 L1TxDA/PA9 L1RxDA/PA8 TIN1/L1RCLKA/BRGO1/CLK1/PA7 TOUT1/CLK2/PA6 IRQ2/RSV TIN2/L1TCLKA/BRGO2/CLK3/PA5 IRQ4/KR/RETRY/SPKROUT TOUT2/CLK4/PA4 CR/IRQ3 TIN3/BRGO3/CLK5/PA3 D[0–31] TOUT3/CLK6/PA2 DP[0–3]/IRQ[3–6] TIN4/BRGO4/CLK7/PA1 TOUT4/CLK8/PA0 REJECT1/SPISEL/PB31 SPICLK/PB30 FRZ/IRQ6...
Page 325 Figure 12-2. Signals and Pin Numbers (Part 1)Signals and Pin Numbers (Part 2) V DDSYN /V SSSYN /V SSSYN1 /V DDH /V DDL /V SS /KAPWR T1–V DDSYN RxD1/PA15 1–C18 U1–V SSSYN TxD1/PA14 1–D17 V1–V SSSYN1 PA13 1–E17 F4–V DDH PA12 1–F17 PA11...
Page 326 A0–B19 A[0–31] A1–B18 B9–1 TSIZ0/REG A2–A18 C9–1 TSIZ1 A3–C16 B2–1 A4–B17 F1–1 BURST A5–A17 D2–1 BDIP/GPL_B5 A6–B16 F3–1 A7–A16 C2–1 A8–D15 D1–1 A9–C15 E3–1 A10–B15 H3–1 IRQ2/RSV A11–A15 K1–1 IRQ4/KR/RETRY/SPKROUT A12–C14 F2–1 CR/IRQ3 A13–B14 D0–W14 D[0–31] A14–A14 D1–W12 V3, V5, W4, V4–4 DP[0–3]/IRQ[3–6] A15–D12 D2–W11...
Page 327 System Bus Signals 12.1 System Bus Signals The MPC857T system bus consists of all signals that interface with the external bus. Many of these signals perform different functions, depending on how the user assigns them. The input and output signals in Table 12-1 are identiÞed by their abbreviation. Table 12-1.
Page 328 System Bus Signals Table 12-1. Signal Descriptions (Continued) Name Hard Reset Number Type Description Hi-Z Bidirectional Transfer Acknowledge—Indicates that the slave device Active addressed in the current transaction accepted data sent by the Pull-up master (write) or has driven the data bus with valid data (read). This is an output when the PCMCIA interface or memory controller controls the transaction.
Page 329 System Bus Signals Table 12-1. Signal Descriptions (Continued) Name Hard Reset Number Type Description D[0–31] Hi-Z Bidirectional Data Bus—Bidirectional three-state bus, provides the Figure 12-2 Three-state general-purpose data path between the MPC857T and all other devices. The 32-bit data path can be dynamically sized to support 8-, 16-, or 32-bit transfers.
Page 330 System Bus Signals Table 12-1. Signal Descriptions (Continued) Name Hard Reset Number Type Description Hi-Z Bidirectional Bus Request—Asserted low when a possible master is requesting ownership of the bus. When the MPC857T is conﬁgured to work with the internal arbiter, this signal is conﬁgured as an input.
Page 331 System Bus Signals Table 12-1. Signal Descriptions (Continued) Name Hard Reset Number Type Description High Output Write Enable 0—Output asserted when a write access to an BS_B0 external slave controlled by the GPCM is initiated by the IORD MPC857T. WE0 is asserted if D[0–7] contains valid data to be stored by the slave device.
Page 332 System Bus Signals Table 12-1. Signal Descriptions (Continued) Name Hard Reset Number Type Description GPL_A0 High Output General-Purpose Line 0 on UPMA—This output reﬂects the GPL_B0 value speciﬁed in the UPMA when an external transfer to a slave is controlled by the UPMA. General-Purpose Line 0 on UPMB—This output reﬂects the value speciﬁed in the UPMB when an external transfer to a slave is controlled by the UPMB.
Page 333 System Bus Signals Table 12-1. Signal Descriptions (Continued) Name Hard Reset Number Type Description SRESET Open-drain Soft Reset—Asserting this open drain line puts the MPC857T in soft reset state. XTAL Analog Analog This output is one of the connections to an external crystal for Driving Output the internal oscillator circuitry.
Page 334 System Bus Signals Table 12-1. Signal Descriptions (Continued) Name Hard Reset Number Type Description IP_A(1) Hi-Z Input Input Port A 1—This input signals is monitored by the MPC857T and its value is reﬂected in the PIPR and PSCR of the PCMCIA UTPB_Aux[1] interface.
Page 335 System Bus Signals Table 12-1. Signal Descriptions (Continued) Name Hard Reset Number Type Description IP_A(6) Hi-Z Input Input Port A 6—This input signals is monitored by the MPC857T and its value is reﬂected in the PIPR and PSCR of the PCMCIA UTPB_Aux[6] interface.
Page 336 System Bus Signals Table 12-1. Signal Descriptions (Continued) Name Hard Reset Number Type Description IP_B3 Bidirectional Input Port B 3—The MPC857T monitors this input; its value and IWP2 Table 12-2 changes are reported in the PIPR and PSCR of the PCMCIA interface.
Page 337 System Bus Signals Table 12-1. Signal Descriptions (Continued) Name Hard Reset Number Type Description OP(0) Output Output Port 0—This output signals is generated by the MPC857T as a result of a write to the PGCRA register in the MII-TXD0 PCMCIA interface. UtpClk_Aux MII-TXD0- Media independent interface transmit data 0.
Page 338 System Bus Signals Table 12-1. Signal Descriptions (Continued) Name Hard Reset Number Type Description Hi-Z Input Address Strobe—Input driven by an external asynchronous master to indicate a valid address on A[0–31]. The MPC857T memory controller synchronizes AS and controls the memory device addressed under its control.
Page 339 System Bus Signals Table 12-1. Signal Descriptions (Continued) Name Hard Reset Number Type Description PA[4] Hi-Z Bidirectional General-Purpose I/O Port A Bit 4—Bit 4 of the general-purpose CLK4 I/O port A. TOUT2 CLK4—One of eight clock inputs that can be used to clock SCCs and SMCs.
Page 340 System Bus Signals Table 12-1. Signal Descriptions (Continued) Name Hard Reset Number Type Description PB[26] Hi-Z Bidirectional General-Purpose I/O Port B Bit 26—Bit 26 of the I2CSCL (Optional: general-purpose I/O port B. BRGO2 Open-drain) I2CSCL—I C serial clock pin. Bidirectional; should be conﬁgured as an open-drain output.
Page 341 System Bus Signals Table 12-1. Signal Descriptions (Continued) Name Hard Reset Number Type Description PB[17] Hi-Z Bidirectional General-Purpose I/O Port B Bit 17—Bit 17 of the L1ST3 (Optional: general-purpose I/O port B. RTS3 Open-drain) L1ST3—One of four output strobes that can be generated by the PHREQ[1] serial interface.
Page 342 System Bus Signals Table 12-1. Signal Descriptions (Continued) Name Hard Reset Number Type Description PC[10] Hi-Z Bidirectional General-Purpose I/O Port C Bit 10—Bit 10 of the general-purpose I/O port C. TGATE1 CD1—Carrier detect modem line for SCC1. TGATE1—Timer 1/timer 2 gate signal. PC[9] Hi-Z Bidirectional...
Page 343 System Bus Signals Table 12-1. Signal Descriptions (Continued) Name Hard Reset Number Type Description PD[11] Hi-Z Bidirectional General-Purpose I/O Port D Bit 11—Bit 11 of the RXENB general-purpose I/O port D. MII-TX-ERR RXENB—Receive enable output signal. MII-TX-ERR—Media independent interface transmit error PD[10] Hi-Z Bidirectional...
Page 344 System Bus Signals Table 12-1. Signal Descriptions (Continued) Name Hard Reset Number Type Description Pulled up Input Controls the scan chain test mode operations. Input Input serial data for either the scan chain logic or the Pulled up DSDI development port and determines the operating mode of the development port at reset.
Page 345 Active Pull-Up Buffers Table 12-2. Configuration-Dependent Signal Behavior during Reset Signal Function Determined at Reset by… Signal Behavior SRESET HRESET (or PORESET) Previous SIUMCR default values only BDIP/GPL_B5 BDIP: high impedance programming of GPL_B5: high SIUMCR RSV/IRQ2 IRQ2: high impedance RSV: high CR/IRQ3 IRQ3: high impedance...
Page 346 Active Pull-Up Buffers if the voltage ever dips below the logic high threshold while the buffer is enabled as an output, the buffer will reactivate. Further, external logic must not attempt to drive these signals low while active pull-up buffers are enabled as outputs, because the buffers will reactivate and drive high, resulting in a buffer Þght and possible damage to the MPC857T, to the system, or to both.
Page 347 Internal Pull-Up and Pull-Down Resistors The purpose of active pull-up buffers is to allow access to zero wait-state logic that drives a shared signal on the clock cycle immediately following a cycle in which the signal is driven by the MPC857T. In other words, it eliminates the need for a bus turn-around cycle. 12.3 Internal Pull-Up and Pull-Down Resistors The TMS and TRST pins have internal pull-up resistors.
Page 348 Recommended Basic Pin Connections 12.4.1.1 Bus Control Signals and Interrupts Signals with open-drain buffers and active pull-up buffers (HRESET, SRESET, TEA, TS, TA, BI, and BB) must have external pull-up resistors. Some other input signals do not absolutely require a pull-up resistor, as they may be actively driven by external logic.
Page 349 Signal States during Reset 12.4.3 Unused Inputs In general, pull-up resistors should be used on any unused inputs to keep them from oscillating. For example, if PCMCIA is not used, the PCMCIA input pins (WAIT_A, WAIT_B, IP_A[0Ð8], IP_B[0Ð8]) should have external pull-up resistors. However, unused pins of port A, B, C, or D can be conÞgured as outputs, and, if they are conÞgured as outputs they do not require external terminations.
Page 350 Signal States during Reset 12-28 MPC857T PowerQUICC User’s Manual...
Page 351 Chapter 13 External Bus Interface The MPC857T bus is a synchronous, burstable bus that can support multiple masters. Signals driven on this bus are required to make the setup and hold time relative to the bus clockÕs rising edge. The MPC857T architecture supports byte, half-word, and word operands allowing access to 8-, 16-, and 32-bit data ports through the use of synchronous cycles controlled by the size outputs (TSIZ0, TSIZ1).
Page 352 Bus Interface Signal Descriptions The MPC857TÕs address bus speciÞes the address for the transfer and its data bus transfers the data. Control signals indicate the beginning of the cycle and the type of cycle, as well as the address space and size of the transfer. The selected device controls cycle length with signal(s) used to terminate the cycle.
Page 353 Bus Interface Signal Descriptions A[0–31] BURST TSIZ[0–1] Address AT[0–3] Transfer Attributes BDIP Transfer Start KR/RETRY Reservation Protocol D[0–31] DP[0–3] Data Transfer Cycle Termination Arbitration Figure 13-2. MPC857T Bus Signals Table 13-1 describes each signal; detailed descriptions can be found in subsequent sections. Table 13-1.
Page 354 Bus Interface Signal Descriptions Table 13-1. MPC857T Signal Overview (Continued) Signal Pins Active I/O Description BURST Driven by the MPC857T along with the address when it owns the external bus. Burst Driven low indicates that a burst transfer is in progress. Driven high indicates that Transfer the current transfer is not a burst.
Page 355 Bus Interface Signal Descriptions Table 13-1. MPC857T Signal Overview (Continued) Signal Pins Active I/O Description Data D[0–31] High The data bus has the following byte lane assignments: Data Bus Data Byte Byte Lane D[0–7]0 D[8–15]1 D[16–23]2 D[24–31]3 Driven by the MPC857T when it is external bus master and it initiated a write transaction to a slave device.
Page 356 Bus Operations Table 13-1. MPC857T Signal Overview (Continued) Signal Pins Active I/O Description Arbitration Asserting BR when the internal arbiter is enabled indicates that an external Bus Request master is requesting the bus. The MPC857T drives BR when the internal arbiter is disabled. When the internal arbiter is enabled, the MPC857T asserts BG to indicate that Bus Grant an external master may assume bus mastership and begin a bus transaction.
Page 357 Bus Operations 13.4.1 Basic Transfer Protocol The basic transfer protocol deÞnes the sequence of actions required for a complete MPC857T bus transaction. Figure 13-3 shows a simpliÞcation of the basic transfer protocol. Arbitration Address transfer Data transfer Termination Figure 13-3. .Basic Transfer Protocol ¥...
Page 358 Bus Operations MASTER SLAVE Bus Request (BR) Receives Bus Grant (BG) from arbiter Asserts Bus Busy (BB) if no other master is driving Asserts Transfer Start (TS) Drives address and attributes Receives Address Returns data Asserts Transfer Acknowledge (TA) Receives data Figure 13-4.
Page 359 Bus Operations CLKOUT Receive BG and BB negated Assert BB, drive address and assert TS A[–31] TSIZ[0–1], AT[0–3] BURST Data Data is Valid Figure 13-5. Basic Timing: Single-Beat Read Cycle, Zero Wait States Chapter 13. External Bus Interface 13-9...
Page 360 Bus Operations CLKOUT Receive BG and BB negated Assert BB, drive address and assert TS A[–31] TSIZ[0–1], AT[0–3] BURST Data Wait State Data is Valid Figure 13-6. Basic Timing: Single-Beat Read Cycle, One Wait State 13.4.2.2 Single-Beat Write Flow The basic write cycle begins with a bus arbitration, followed by the address transfer, then the data transfer.
Page 361 Bus Operations MASTER SLAVE Bus Request (BR) Receives Bus Grant (BG) from arbiter Asserts Bus Busy (BB) if no other master is driving Asserts Transfer Start (TS) Drives address and attributes Drives data Asserts Transfer Acknowledge (TA) Interrupts data driving Figure 13-7.
Page 362 Bus Operations CLKOUT Receive BG and BB negated Assert BB, drive address and assert TS A[–31] TSIZ[0–1], AT[0–3] BURST Data Data is sampled Figure 13-8. Basic Timing: Single-Beat Write Cycle, Zero Wait States 13-12 MPC857T PowerQUICC User’s Manual...
Page 363 Bus Operations CLKOUT Receive BG and BB negated Assert BB, drive address and assert TS A[–31] TSIZ[0–1], AT[0–3] BURST Data Wait State Data is Sampled Figure 13-9. Basic Timing: Single-Beat Write Cycle, One Wait State The general case of single-beat transfers assumes that external memory has a 32-bit port size.
Page 364 Bus Operations CLKOUT A[–31] A + 2 TSIZ[0–1] BURST Data ABCDEFGH EFGHEFGH Figure 13-10. Basic Timing: Single-Beat, 32-Bit Data Write Cycle, 16-Bit Port Size 13.4.3 Burst Transfers The MPC857T or other synchronous external bus devices use burst transfers to access 16-byte operands.
Page 365 Bus Operations devices that do not support bursting. For this type of cycle, the selected slave device supplies/samples the address of the Þrst word of the burst and asserts the burst-inhibit signal (BI) with TA for the Þrst transfer of the burst access. The MPC857T responds by terminating the burst and accessing the rest of the 16-byte block, using three read/write cycles (each one for a word) for a 32-bit port-width slave, seven read/write cycles for a 16-bit port-width slave, or Þfteen read/write cycles for a 8-bit port-width slave.
Page 366 Bus Operations In the case of 32-bit port size, the burst includes 4 beats. When the port size is 16 bits and controlled by the internal memory controller, the burst includes 8 beats. When the port size is 8 bits and controlled by the internal memory controller, the burst includes 16 beats. The MPC857T bus supports critical data Þrst access for Þxed-size burst.
Page 367 Bus Operations MASTER SLAVE Bus Request (BR) Receives Bus Grant (BG) from arbiter Asserts Bus Busy (BB) if no other master is driving Asserts Transfer Start (TS) Drives address and attributes Drives BURST asserted Receives address Asserts Burst Data in Progress (BDIP) Returns data Asserts Transfer Acknowledge (TA) Receives data...
Page 368 Bus Operations CLKOUT A[–31], AT[0–3] TSIZ[0–1] BURST Last Beat Expects Another Data BDIP Data Data is Data is Data is Data is Valid Valid Valid Valid Figure 13-12. Burst-Read Cycle: 32-Bit Port Size, Zero Wait State 13-18 MPC857T PowerQUICC User’s Manual...
Page 369 Bus Operations CLKOUT A[–31], AT[0–3] TSIZ[0–1] BURST Last Beat Expects Another Data BDIP Data Data is Data is Data is Data is Valid Valid Valid Valid Wait State Figure 13-13. Burst-Read Cycle: 32-Bit Port Size, One Wait State Chapter 13. External Bus Interface 13-19...
Page 370 Bus Operations CLKOUT A[–31], AT[0–3] TSIZ[0–1] BURST Last Beat Expects Another Data BDIP Data Data is Data is Data is Data is Valid Valid Valid Valid Wait State Figure 13-14. Burst-Read Cycle: 32-Bit Port Size, Wait States between Beats 13-20 MPC857T PowerQUICC User’s Manual...
Page 371 Bus Operations CLKOUT A[–31], AT[0–3] TSIZ[0–1] BURST BDIP Data Figure 13-15. Burst-Read Cycle: 16-Bit Port Size, One Wait State between Beats Chapter 13. External Bus Interface 13-21...
Page 372 Bus Operations MASTER SLAVE Bus Request (BR) Receives Bus Grant (BG) from arbiter Asserts Bus Busy (BB) if no other master is driving Asserts Transfer Start (TS) Drives address and attributes Drives BURST asserted Receives address Drives data Asserts burst data in progress (BDIP) Asserts Transfer Acknowledge (TA) Drives data BDIP asserted...
Page 373 Bus Operations CLKOUT A[–31], AT[0–3] TSIZ[0–1] BURST Last beat Will drive another data BDIP Data Data is Data is Data is Data is sampled sampled sampled sampled Figure 13-17. Burst-Write Cycle: 32-Bit Port Size, Zero Wait States Figure 13-18 shows an attempted burst read to a slave device that does not support bursting. The slave acknowledges the Þrst transfer and also asserts the burst-inhibit signal (BI).
Page 374 Bus Operations CLKOUT A[–27] A[28–29] n+1 Mod 4 n+2 Mod 4 n+3 Mod 4 A[30–31] TSIZ[0–1] BURST BDIP Data Figure 13-18. Burst-Inhibit Cycle: 32-Bit Port Size 13.4.5 Alignment and Data Packing on Transfers The MPC857T external bus supports only natural address alignment: ¥...
Page 375 Bus Operations Misaligned accesses performed by the core are broken into multiple bus accesses with natural alignment. Misaligned accesses performed by external masters are not supported. The MPC857T transfers operands through its 32-bit data port. If the transfer is controlled by the internal memory controller, the MPC857T can support 8- and 16-bit data port sizes.
Page 376 Bus Operations Interface Output Register D[0–7] D[8–15] D[16–23] D[24–31] 32-Bit Port Size 16-Bit Port Size 8-Bit Port Size Figure 13-20. Interface to Different Port Size Devices Table 13-2 lists the bytes required on the data bus for read cycles. Table 13-2. Data Bus Requirements for Read Cycles Address 32-Bit Port 16-Bit Port...
Page 377 Bus Operations accesses. Table 13-3. Data Bus Contents for Write Cycles Address External Data Bus Pattern Transfer TSIZ[0–1] Size D[0–7] D[8–15] D[16–D3] D[24–31] Byte — — — — — — — — Half-Word — — Word — denotes a byte not required during that read cycle. 13.4.6 Arbitration Phase The external bus design provides for a single bus master at any one time, either the MPC857T or an external device.
Page 378 Bus Operations Requesting Device Arbiter Request the bus Assert BR Grant bus Assert BG Request the bus 1. Wait for BB to be negated 2. Assert BB to become next master 3. Negate BR Terminate arbitration Negate BG (or keep it asserted to park bus master) Operate as bus master Perform data transfer...
Page 379 Bus Operations 13.4.6.3 Bus Busy (BB) BB indicates that the current master is using the bus. New masters should not begin a transfer until BB is deasserted. The bus master should not relinquish or negate BB until it completes its transfer. To avoid contention on BB, masters should three-state BB when it gets a logical 1 value.
Page 380 Bus Operations CLKOUT ADDR/ATTR Master 0 Master 0 Master 1 ‘turns on’ negates ‘turns on’ drives drives signals ‘turns off’ signals Figure 13-23. Bus Arbitration Timing Diagram The MPC857T can be conÞgured at system reset to use the internal bus arbiter. In this case, the MPC857T is parked on the bus.
Page 381 Bus Operations BB = 0 External owner MPC857T BB = three-state Internal master BG = 0 with higher priority than the External master external device requires requests bus the bus BR = 1 BB = 0 External master release bus 80 owner Idle BB = three-state...
Page 382 Bus Operations 13.4.7.2 Address Bus The 32-bit address bus, A[0Ð31], is byte addressable, so each address can address one or more bytes. A[0] is the msb. The address and its attributes are driven on the bus with TS; they remain valid until the bus master receives a transfer acknowledge from the slave. To distinguish an individual byte, the slave device must observe the TSIZ signals.
Page 383 Bus Operations Address type signals reßect the current status of the master originating the access, not necessarily the status in which the original access to this location has occurred. An example of this situation is when a modiÞed data cache block is copied back after the privilege level of the processor has been changed since the last access to the same cache block.
Page 384 Bus Operations Table 13-5. Address Types Definition (Continued) Core/ User/ Instruction Reservation/ Program Reservatio Address Space STS TS Superviso / Data Program Trace n (RSV) Deﬁnitions (AT0) r(AT1) (AT2) Trace (AT3) (PTR) Core-initiated, show cycle address instruction, program trace, supervisor mode Core-initiated, show cycle address instruction, supervisor mode...
Page 385 Bus Operations ¥ RSV is low when the following is true: Ñ AT0 = 0 (Core access) Ñ AT2 = 1 (Data) Ñ AT3 = 0 (Reservation) 13.4.7.3.5 Burst Data in Progress (BDIP) The master asserts BDIP to indicate to the slave that another data beat follows the current data beat.
Page 386 Bus Operations External Bus Slave 1 MPC857T Termination Signals (TA, TEA, BI) Slave 2 Figure 13-25. Termination Signals Protocol Basic Connection CLKOUT A[–31] Slave 1 Slave 2 TSIZ[0–1] Data TA, BI, TEA Slave 1 Slave 1 Slave 2 Slave 2 allowed to negates allowed to...
Page 387 Bus Operations reservation loss on a remote bus only when it has issued a STWCX cycle to that address. That is, the reservation loss indication comes as part of the STWCX cycle, which avoids the need for fast memory reservation loss indication signals between each remote bus and each PowerPC master.
Page 388 Bus Operations MPC857T External Bus External Bus Interface Other Master AT[0–3], RSV, R/W, TS Iwarx A[0–31] Enable External stwcx. Access Reservation Logic CLKOUT Figure 13-27. Reservation On Local Bus The MPC860 samples CR at the rising edge of CLKOUT. When CR is asserted, the reservation ßag is reset.
Page 389 Bus Operations External Bus (Local Bus) MPC857T A[–31] External Bus Interface AT[0–3], RSV, R/W, TS Buses’ Interface Master in the Remote Bus Write to the Reserved Location Remote Bus Figure 13-28. Reservation on Multilevel Bus Hierarchy In this case, the busesÕ interface block implements a reservation ßag for the local bus master.
Page 390 Bus Operations To properly control termination of a bus cycle for a bus error, TEA must be asserted at the same time or before TA is asserted. Once TEA is sampled as asserted, it should be negated before the next rising edge to avoid inßuencing the next initiated bus cycle. TEA is an open-drain pin that allows the wire-OR of different sources of error generation.
Page 391 Bus Operations CLKOUT BG (Output) Allow external master to gain the bus A[–31] TSIZ[0–1] BURST Data RETRY Figure 13-29. Retry Transfer Timing–Internal Arbiter Chapter 13. External Bus Interface 13-41...
Page 392 Bus Operations CLKOUT BR (Output) Allow external master to gain the bus A[–31] TSIZ[0–1] BURST Data RETRY Figure 13-30. Retry Transfer Timing–External Arbiter When the MPC857T initiates a burst access, the bus interface only recognizes the RETRY assertion as a retry termination if it detects it before the slave device acknowledges the Þrst data beat.
Page 393 Bus Operations CLKOUT BG (Output) Allow external master to gain the bus A[–31] TSIZ[0–1] BURST Data RETRY If asserted will cause transfer error Figure 13-31. Retry on Burst Cycle If a burst access is acknowledged on its Þrst beat with a normal TA, but with BI asserted, the following single-beat transfers initiated by the MPC857T to complete the 16 byte transfers process the RETRY signal assertion as a TEA.
Page 394 Bus Operations Table 13-6 summarizes how the MPC857T recognizes the termination signals provided by the slave device that is addressed by the initiated transfer. Table 13-6. Termination Signals Protocol RETRY/KR Action Transfer error termination Normal transfer termination Retry transfer termination/kill reservation 13-44 MPC857T PowerQUICC User’s Manual...
Page 395 Chapter 14 Clocks and Power Control The MPC857T clock system provides many different clocking options for all on-chip and external devices. For its clock sources, the MPC857T contains phase-locked loop and crystal oscillator support circuitry. The phase-locked loop circuitry can be used to provide a high-frequency system clock from a low-frequency external source.
Page 396 The Clock Module MODCK[1:2] V DDSYN EXTCLK SPLL vcoout gclk2 oscclk gclk/ gclk2 2:1 MUX SCCR (÷4 OR ÷16) [TBS] gclk1c/ gclk2c Low-Power Dividers gclk1_50/ gclk2_50 Clock Drivers brgclk tbclk syncclk CLKOUT CLKOUT Driver Time Base and tmbclk Decrementer Driver SCCR[RTSEL] SCCR[RTDIV] ÷4...
Page 397 The Clock Module Crystal V DD 0.1 µF V SSSYN V SSSYN1 V DDSYN EXTAL XTAL OSCM SPLL CLKOUT EXTCLK Figure 14-2. Clock Module Components 14.2.1 External Reference Clocks The MPC857T has two input clock sources, provided at the EXTCLK pin or at the EXTAL and XTAL pins.
Page 398 The Clock Module A typical conÞguration uses a canned oscillator (4 MHz or 50 MHz) with the EXTCLK input selected as OSCCLK, and a 32.768 kHz or 38.4 kHz crystal at EXTAL and XTAL to provide PITRTCLK. 14.2.1.1 Off-Chip Oscillator Input (EXTCLK) The external clock input EXTCLK is generated from an external source, which is typically a canned oscillator.
Page 399 The Clock Module Crystal EXTAL XTAL OSCM 32 kHz: R1=20MW, R2=330kW, C1=20pF, C2=20pF 4 MHz: R1=10MW, R2=1kW, C1=47 pF, C2=56 pF Figure 14-3. Crystal Circuit Examples 14.2.2 System PLL The programmable phase-locked loop, called the system phase-locked loop (SPLL) in the MPC857T, generates the overall system operating frequency in integer multiples of the input clock frequency.
Page 400 The Clock Module The OSCCLK signal goes to the phase comparator that controls the direction in which the charge pump drives the voltage across the external Þlter capacitor (XFC). Direction is based on whether the feedback signal phase lags or leads the reference signal. The output of the charge pump drives a voltage-controlled oscillator (VCO).
Page 401 The Clock Module Note that under no condition should the voltage on MODCK1 and MODCK2 exceed the power supply voltage VDDH applied to the part. At power-on reset, before the PLL achieves lock, no internal or external clocks are generated by the MPC857T, which may cause higher than normal static current during the short period of stabilization.
Page 402 Clock Signals ¥ VDDSYNÑThe power supply pin for the analog SPLL circuitry. For requirements concerning this power supply, refer to Section 14.4.3, ÒClock Synthesizer Power (VDDSYN, VSSSYN, VSSYN1). ¥ VSSSYN and VSSSYN1ÑGround reference pins for the analog SPLL circuitry. For requirements concerning this ground reference, refer to Section 14.4.3, ÒClock Synthesizer Power (VDDSYN, VSSSYN, VSSYN1).
Page 403 Clock Signals Table 14-3. Functionality Summary of the Clocks Clock Description GCLK1C/GCLK2C Basic clocks supplied to the core, the data and instruction caches, and MMUs. GCLK1/GCLK2 Basic clocks supplied to the SIU, clock module, CP, and most other features in the CPM GCLK1_50/GCLK2_50 Optionally divided versions of GCLK1/GCLK2, which are used to clock the GPCM and UPM in the memory controller and to provide the CLKOUT output for the external bus.
Page 404 Clock Signals VCOOUT SYNCCLK DFSYNC BRGCLK DFBRG GCLK1C CPM and Sleep (Refresh Mode Timers) GCLK2C Phase GCLK2 DFNH UPM and GCLK1 GCLK1_50 Timer DFNL EBDF Module, Phase Core, GCLK2_50 and CPM Low-Power CLKOUT Mode Figure 14-5. . Clock Dividers 14.3.1.1 The Internal General System Clocks (GCLK1C, GCLK2C, GCLK1, GCLK2) The GCLKxC and GCLKx signals are referred to here collectively as GCLKx.
Page 405 Clock Signals The high frequency is generated by using the DFNH Þeld in the SCCR and it is used in normal high and doze high mode. The low frequency is generated using the DFNL Þeld in the SCCR and it is used in normal low and doze low mode. The DFNH and DFNL dividers are cleared by HRESET, and therefore GCLKx defaults to VCOOUT.
Page 406 Clock Signals GCLK1 GCLK2 GCLK1_50 (EBDF=00) GCLK2_50 (EBDF=00) CLKOUT (EBDF=00) GCLK1_50 (EBDF=01) GCLK2_50 (EBDF=01) CLKOUT (EBDF=01) Figure 14-8. Memory Controller and External Bus Clocks Timing Diagram for EBDF=0 and EBDF=1 If SCCR[EBDF]=0, the duty cycle of both GCLK1_50 and GCLK2_50 is 50%. However, if SCCR[EBDF]=1, the duty cycle of GCLK2_50 is 50%, but the duty cycle of GCLK1_50 is 37.5%, as shown in Figure 14-8.
Page 407 Clock Signals GCLK1 GCLK2 GCLK1_50 (EBDF=00) GCLK2_50 (EBDF=00) CLKOUT (EBDF=00) GCLK1_50 (EBDF=01) GCLK2_50 (EBDF=01) CLKOUT (EBDF=01) Figure 14-9. Memory Controller and External Bus Clocks Timing Diagram for (CSRC=0 and DFNH=1) or (CSRC=1 and DFNL=0) The frequency of GCLK1_50 and GCLK2_50 are effected both by the SCCR[DFNH] and SCCR[DFNL] dividers and by the SCCR[EBDF] divider.
Page 408 Clock Signals 14.3.1.3 CLKOUT Special Considerations: 1:2:1 Mode To enable synchronization of a system to the EXTCLK signal while still allowing the internal circuits of the MPC857T to operate at an increased frequency, it is necessary to maintain synchronization of the EXTCLK and CLKOUT signal. SpeciÞcally, this operation entails: ¥...
Page 409 Clock Signals and synchronize asynchronous external signals provided to these ports. SYNCCLK allows the serial interface, serial communication controller, and serial management controllers to continue operating at a Þxed frequency, even when the rest of the MPC857T is operating at a reduced frequency.
Page 410 Power Distribution The MODCK[1-2] state at PORESET deassertion determines the input clock source and prescaler value for PITRTCLK. These values can be changed after reset by manipulating the associated bits in the SCCR. Table 14-4. PITRTCLK Configuration at PORESET PITRTCLK Prescaler PITRTCLK Input Source MODCK [1:2] SCCR[RTDIV]...
Page 411 Power Distribution I/O Pad Internal Logic OSCM, PIT, TEXP RTC, TB, Clock Drivers DEC, SCCR, PLPRCR, KAPWR and RSR Analog Clock Control SPLL and Digital SPLL V DDH V DDL V DDSYN Figure 14-12. MPC857T Power Rails A complete tabulation of modules and power supplies is given in Table 14-6. Table 14-6.
Page 412 Power Control (Low-Power Modes) 14.4.2 Internal Logic Power (VDDL) The internal logic can be fed by the same 3.3V source which powers VDDH. VDDL is identiÞed as a separate power supply only to facilitate power measurements. 14.4.3 Clock Synthesizer Power (VDDSYN, VSSSYN, VSSYN1) To improve stability, the power supply pins for the SPLL are uniquely identiÞed in order to allow special Þltration to be provided for them.
Page 413 Power Control (Low-Power Modes) Low-power modes are controlled in the PLPRCR[LPM] and PLPRCR[CSRC]. Events can cause automatic changes from one low-power mode to another. These events include software-initiation (through the MSR[POW]), CPM activity, internal interrupt sources, external interrupt sources, and resets. These events are enabled in the SCCR[PRQEN]. The characteristics of each low-power mode are summarized in Table 14-7.
Page 414 Power Control (Low-Power Modes) A state diagram describing transitions between the various low-power modes is shown in Figure 14-13. CPM_ACT | MSRPOW | Interrupt | (¬ CSRC) Software-Initiated Normal Low ¬ CPM_ACT & (¬ MSRPOW) & LPM=00, CSRC=1 (Interrupt Cleared) & CSRC Software-Initiated Doze Low LPM=01, CSRC=1...
Page 415 Power Control (Low-Power Modes) 14.5.1 Normal High Mode Normal high mode is the default mode of the MPC857T. In this mode, the GCLKx frequency is determined by SCCR[DFNH], and all modules of the MPC857T are enabled. For more information about SCCR[DFNH], refer to Section 14.3.1.1, ÒThe Internal General System Clocks (GCLK1C, GCLK2C, GCLK1, GCLK2).
Page 416 Power Control (Low-Power Modes) Doze high mode selected PLPRCR[CSRC]=0, MSR[POW]=1, PLPRCR[LPM]=01. In doze high mode, the GCLKx frequency is determined by SCCR[DFNH]. For more information about SCCR[DFNH], see Section 14.3.1.1, ÒThe Internal General System Clocks (GCLK1C, GCLK2C, GCLK1, GCLK2).Ó Note also that PLPRCR[TMIST] should be cleared before entering doze high mode;...
Page 417 Power Control (Low-Power Modes) Upon resumption of processing in normal high or low mode, the MPC857T jumps to the external interrupt vector to process the interrupt source. When the core returns from the exception handler via rﬁ , it resumes processing from the instruction following that which initiated entry into doze mode.
Page 418 Power Control (Low-Power Modes) Deep-sleep mode is selected if PLPRCR[LPM]=11 and PLPRCR[TEXPS]=1. Note also that PLPRCR[TMIST] should be cleared before entering deep-sleep mode; for more information, see Section 14.5.8, ÒTMIST: Facilitating Nesting of SIU Timer Interrupts.Ó Note that the RTC, PIT, TB, and DEC operate in deep-sleep mode only if their timing reference is OSCM.
Page 419 Power Control (Low-Power Modes) signal deasserts. This signal deassertion can be used externally to shut down the VDDH, VDDL, and VDDSYN power supplies. In performing this operation, TEXP should be deasserted by setting PLPRCR[LPM]=11 and clearing PLPRCR[TEXPS] (by writing 1). The TEXP signal can also be used to enable automatic or externally-initiated wakeup from power-down mode.
Page 420 Power Control (Low-Power Modes) PLPRCR[TEXPS] is asserted by the MPC857T when the real-time clock or timebase time value matches the value programmed in its associated alarm register or when the periodic interrupt timer or decrementer decrements their value to zero, or when the HRESET signal is externally asserted.
Page 421 Clock and Power Control Registers 14.5.8 TMIST: Facilitating Nesting of SIU Timer Interrupts It is often desirable, within an interrupt service routine, to clear the source of the interrupt at the beginning of the routine, in order to facilitate nesting of interrupts. However, if normal low mode is enabled, clearing an interrupt source can cause transition into normal low mode, which may not be desired.
Page 422 Clock and Power Control Registers Table 14-8 describes SCCR Þelds. Table 14-8. SCCR Field Descriptions Bits Name Description — Reserved, should be cleared. 1–2 Clock output module. This ﬁeld controls the output buffer strength of the CLKOUT pin. When both bits are set, the CLKOUT pin is held in the high state.
Page 423 Clock and Power Control Registers Table 14-8. SCCR Field Descriptions (Continued) Bits Name Description 17–18 DFSYN Division factor for the SYNCCLK. This ﬁeld sets the VCOOUT frequency division factor for the SYNCCLK signal. Changing the value of this ﬁeld does not result in a loss-of-lock condition. This ﬁeld is cleared by a power-on or hard reset.
Page 424 Clock and Power Control Registers Field — HRESET — Addr (IMMR&0xFFFF0000) + 284 Field SPLSS TEXPS — TMIST — CSRC CSR LOLRE FIOPD — HRESET — — — — Addr (IMMR&0xFFFF0000) + 286 NOTE: HRESET is hard reset and POR is power-on reset. Depends on the combination of MODCK1and MODCK2.
Page 425 Clock and Power Control Registers Table 14-9. PLPRCR Field Descriptions (Continued) Bits Name Description TMIST Timers interrupt status. Cleared at reset. Set when a real-time clock, periodic interrupt timer, timebase, or decrementer interrupt occurs. This bit is cleared by writing a 1; writing a zero has no effect.
Page 426 Clock and Power Control Registers 14-32 MPC857T PowerQUICC User’s Manual...
Page 427 Chapter 15 Memory Controller The memory controller is responsible for controlling a maximum of eight memory banks shared between a general-purpose chip-select machine (GPCM) and a pair of sophisticated user-programmable machines (UPMs). It supports a glueless interface to SRAM, EPROM, ßash EPROM, regular DRAM devices, self-refresh DRAMs, extended data output DRAM devices, synchronous DRAMs, and other peripherals.
Page 428 Features Ñ Write-protection capability Ñ Address types protection for memory bank accesses by internal masters Ñ Control signal generation machine selection on a per-bank basis Ñ Support for external master access to memory banks Ñ Synchronous and asynchronous external masters support ¥...
Page 429 Features Figure 15-1 is a block diagram of the memory controller. Address [0–16], AT[0–2] Address Latch Multiplexer BADDR[28–30] Incrementer Base Register (BR) Base Register (BR) NA and AMX Fields in RAM Word Option Register (OR) Option Register (OR) Attributes SCY[0–3] CS[0–7] Expired WE[0–3]...
Page 430 Basic Architecture 15.2 Basic Architecture The memory controller consists of three basic machines: ¥ General-purpose chip-select machine (GPCM) ¥ User-programmable machine A (UPMA) ¥ User-programmable machine B (UPMB) Each bank can be assigned to any one of these machines via the BR x [MS] bits as shown in Figure 15-2.
Page 431 Basic Architecture can be enabled for a speciÞc memory bank in the base register. The type of parity is deÞned in the system interface unit module conÞguration register (SIUMCR), which is explained in Section 10.4.2, ÒSIU Module ConÞguration Register (SIUMCR).Ó Each memory bank can be selected for read-only or read/write operation.
Page 432 Chip-Select Programming Common to the GPCM and UPM cycles. The UPM RAM pattern run by the memory controller is selected according to the type of external access transacted. At every clock cycle, the logical value of the external signals speciÞed in the RAM array is output on the corresponding UPM pins. See Figure 15-4.
Page 433 Chip-Select Programming Common to the GPCM and UPM 15.3.1 Address Space Programming Each bank has an option register (ORx) and a base register (BRx), which contains a V bit that indicates that the information for the chip-select is valid. Each base register deÞnes the starting address of its memory bank and each option register deÞnes the attributes for its memory bank.
Page 434 Chip-Select Programming Common to the GPCM and UPM Table 15-2. Access Granularities for Predefined Port Sizes Bytes Half Words Predeﬁned Words (on Word Port Size Boundaries) Even Even Ö Ö 8-bit — — — Ö Ö Ö (on D[0–15]) 16-bit —...
Page 435 Register Descriptions 15.4 Register Descriptions The following sections describe the registers used by the memory controller. 15.4.1 Base Registers (BR x ) The base registers (BR0ÐBR7) contain the base address and address types that the memory controller uses to compare the value on the address bus with the current address accessed. It also includes a memory attribute and selects the machine for memory operation handling.
Page 436 Register Descriptions Table 15-3 describes BRx Þelds. Table 15-3. BR x Field Descriptions Bits Name Description 0–16 Base address. Compared to A[0–16]to determine if a memory bank controlled by the memory controller is being accessed by an internal or external bus master. Used in conjunction with ORx[AM]. 17–19 AT Address type.
Page 437 Register Descriptions 10 11 Field Reset 0000_0000_0000_0000 Addr (IMMR & FFFF0000) + 0x104 (OR0), 0x10C (OR1), 0x114 (OR2), 0x11C (OR3), 0x124 (OR4), 0x12C (OR5), 0x134 (OR6), 0x13C (OR7) 17 18 19 24 25 26 27 Field CSNT/SAM ACS/G5LA,G5LS BIH SETA TRLX EHTR —...
Page 438 Register Descriptions Figure 15-4 describes ORx Þelds. Table 15-4. OR x Field Descriptions Bits Name Description 0–16 Address mask. This read/write ﬁeld independently masks bits A[0–16] on the address bus so external devices of different size address ranges can be used. AM bits can be set or cleared in any order, allowing a resource to reside in more than one area of the address map.
Page 439 Register Descriptions Table 15-4. OR x Field Descriptions (Continued) Bits Name Description TRLX Timing relaxed (GPCM only) 0 Timing is not relaxed. 1 In addition to the timing parameters programmed in other ORx ﬁelds, timing is further relaxed. See the effect of TRLX in Table 15-11. TRLX also doubles the wait-states programmed in SCY. EHTR Extended hold time on read.
Page 440 Register Descriptions Field PTxE — — Reset 0000_0000_0000_0000 Addr (IMMR & FFFF0000) + 0x170 Field G0CLx GPLx4DIS RLFx WLFx TLFx Reset 0000 0000 0000 Addr (IMMR & FFFF0000) + 0x172 Figure 15-10. Machine A Mode Register/Machine B Mode Registers (M x MR) Table 15-6 describes bits for MAMR/MBMR.
Page 441 Register Descriptions Table 15-6. M x MR Field Descriptions (Continued) Bits Name Description 13–14 Disable timer period. Guarantees a minimum time between accesses to the same memory bank if it is controlled by the UPMx. This function can be used to guarantee a minimum RAS precharge time.
Page 442 Register Descriptions Field — — Reset 0000_0000_0000_0000 Addr (IMMR & FFFF0000) + 0x168 Field — MCLF — Reset 0000_0000_0000_0000 Addr (IMMR & FFFF0000) + 0x16A Figure 15-11. Memory Command Register (MCR) Table 15-7 describes MCR Þelds. Table 15-7. MCR Field Descriptions Bits Name Description...
Page 443 Register Descriptions Field Reset 0000_0000_0000_0000 Address (IMMR & FFFF0000) + 0x17C Field Reset 0000_0000_0000_0000 Address (IMMR & FFFF0000) + 0x17E Figure 15-12. Memory Data Register (MDR) Table 15-8 describes MDR. Table 15-8. MDR Field Descriptions Bits Name Description 0–31 Memory data. Contains the RAM array word. 15.4.7 Memory Address Register (MAR) The memory address register contains an address to be driven on the external bus in the case of a...
Page 444 General-Purpose Chip-Select Machine (GPCM) Table 15-9 describes MAR Þelds. Table 15-9. MAR Field Description Bits Name Description 0–31 MA Contains a 32-bit address to be output on the address bus if AMX = 0b11. See Section 15.6.4.1, “RAM Words.” 15.4.8 Memory Periodic Timer Prescaler Register (MPTPR) The memory periodic timer prescaler register (MPTPR) deÞnes the divisor of the external bus clock used as the memory periodic timer input clock.
Page 445 General-Purpose Chip-Select Machine (GPCM) MPC857T- 32-Bit Wide SRAM 128K WE[0–3] WE[0–3] GPL_x1/OE A[15–29] Address D[0–31] Data Figure 15-15. GPCM-to-SRAM Conﬁguration 15.5.1 Timing Conﬁguration If BRx[MS] selects the GPCM, the attributes for the memory cycle are taken from ORx. These attributes include the CSNT, ACS[0Ð1], SCY[0Ð3], TRLX, EHTR, and SETA Þelds. See Table 15-11 for signal behavior and system response.
Page 446 General-Purpose Chip-Select Machine (GPCM) Table 15-11. GPCM Strobe Signal Behavior (Continued) Conﬁguration Signal Behavior Negated Negated Address Address Address Data to OR x SCCR OR x OR x Total Access to CS to OE to WE [TRLX] [EBDF] [CSNT] [ACS] Address/ Address Cycles...
Page 447 General-Purpose Chip-Select Machine (GPCM) MPC857T- Peripheral Address Address Data Data Figure 15-16. GPCM Peripheral Device Interface Figure 15-17 shows CS as deÞned by the setup time required between the address lines and CE. The user can conÞgure ORx[ACS] to specify CS to meet this requirement. Clock Address ACS = 11...
Page 448 General-Purpose Chip-Select Machine (GPCM) MPC857T MEMORY Address Address Data Data Figure 15-18. GPCM Memory Device Interface As Figure 15-20 shows, the timing for CS is the same as for the address lines. The strobes for the transaction are supplied by OE or WE, depending on the transaction direction (read or write).
Page 449 General-Purpose Chip-Select Machine (GPCM) Clock Address ACS = 11 ACS = 10 CSNT = 1 Data Figure 15-20. GPCM Memory Device Basic Timing (ACS ¹ 00, CSNT = 1, TRLX = 0) 15.5.1.3 Relaxed Timing ORx[TRLX] is provided for memory systems that require more relaxed timing between signals.
Page 450 General-Purpose Chip-Select Machine (GPCM) Clock Address ACS = 10 ACS = 11 Data Figure 15-22. GPCM Relaxed-Timing Write (ACS = 1x, SCY = 0, CSNT = 0, TRLX = 1) When TRLX and CSNT are set in a write-memory access, the strobe line, WE is negated one clock earlier than in the normal case.
Page 451 General-Purpose Chip-Select Machine (GPCM) Clock Address ACS = 10 ACS = 11 Data Figure 15-23. GPCM Relaxed-Timing Write (ACS = 1x, SCY = 0, CSNT = 1, TRLX =1) Clock Address Data Figure 15-24. GPCM Relaxed-Timing Write (ACS = 00, SCY = 0, CSNT = 1, TRLX =1) Chapter 15.
Page 452 General-Purpose Chip-Select Machine (GPCM) 15.5.1.4 Output Enable (OE) Timing The timing of the OE is affected only by TRLX. It always asserts and negates on the rising edge of the external bus clock. OE always asserts on the rising clock edge after CS is asserted, and therefore its assertion can be delayed (along with the assertion of CS) by programming TRLX = 1.
Page 453 General-Purpose Chip-Select Machine (GPCM) Clock Address Data Hold Time Long hold time allowed Figure 15-26. GPCM Read Followed by Write (EHTR = 1) Clock Address Data Hold Time Long hold time allowed Figure 15-27. GPCM Read Followed by Read from Different Banks (EHTR = 1) Chapter 15.
Page 454 General-Purpose Chip-Select Machine (GPCM) Clock Address Data Hold Time Figure 15-28. GPCM Read Followed by Read from Same Bank (EHTR = 1) 15.5.2 Boot Chip-Select Operation Boot chip-select operation allows address decoding for a boot ROM before system initialization occurs. The CS0 signal is the boot chip-select output and its operation differs from the other external chip-select outputs on system reset.
Page 455 General-Purpose Chip-Select Machine (GPCM) Table 15-12. Boot Bank Field Values after Reset Register Field Name Value From hard reset conﬁguration word PARE From hard reset conﬁguration word All zeros CSNT 1111 SETA TRLX EHTR 15.5.3 External Asynchronous Master Support Figure 15-29 shows the basic interface between an asynchronous external master and the GPCM to allow connection to static RAM.
Page 456 General-Purpose Chip-Select Machine (GPCM) Clock Address Data Figure 15-30. Asynchronous External Master, GPCM-Handled Memory Access Timing (TRLX = 0) When an external asynchronous master performs accesses a memory device via the GPCM in the memory controller, ORx[CSNT] has no effect. For a comprehensive discussion of external master interfacing, see Section 15.8, ÒExternal Master Support.Ó...
Page 457 User-Programmable Machines (UPMs) Note also the following: ¥ Address incrementing is not provided in this mode. Addresses driven by the MPC857T remain the same throughout the cycle. ¥ The external slave must provide TA for all beats of the burst. 15.6 User-Programmable Machines (UPMs) The two user-programmable machines (UPMs) are ßexible interfaces that connect to a wide range of memory devices.
Page 458 User-Programmable Machines (UPMs) 15.6.1 Requests An internal or external masterÕs request for a memory access initiates one of the following patterns: ¥ Read single-beat pattern (RSS) ¥ Read burst cycle pattern (RBS) ¥ Write single-beat pattern (WSS) ¥ Write burst cycle pattern (WBS) These patterns are described in Section 15.6.1.1, ÒInternal/External Memory Access Requests.Ó...
Page 459 User-Programmable Machines (UPMs) External memory access requests are single-beat and burst reads and writes. A single-beat transfer transfers one operand consisting of a single byte, half word, or word. A burst transfer transfers four words. A single-beat cycle starts with one transfer start and ends with one transfer acknowledge.
Page 460 User-Programmable Machines (UPMs) 15.6.2 Programming the UPM The UPM is a microsequencer that requires microinstructions or RAM words to generate signal timings for different memory cycles. Program the UPMs in the following steps: 1. Write patterns into the RAM array. 2.
Page 461 User-Programmable Machines (UPMs) System Clock CLKOUT GCLK1_50 GCLK2_50 Clock Phase RAM Word 1 RAM Word 2 Figure 15-35. UPM Clock Scheme Two (Division Factor = 2) The state of the external signals may change (if speciÞed in the RAM array) at any edge of GCLK1_50 and GCLK2_50, plus a propagation delay, speciÞed in the MPC857T Hardware Speciﬁcations.
Page 462 User-Programmable Machines (UPMs) Internal System Clock CLKOUT GCLK1_50 GCLK2_50 CST4 CST1 CST2 CST3 CST4 CST1 CST2 CST3 GPL1 G1T4 G1T3 G1T4 G1T4 G1T3 GPL2 G2T4 G2T3 G2T4 G1T4 G2T3 Clock Phase RAM Word 1 RAM Word 2 Figure 15-36. UPM Signals Timing Example One (Division Factor = 1, EBDF = 00) System Clock CLKOUT GCLK1_50...
Page 463 User-Programmable Machines (UPMs) 15.6.4 The RAM Array The RAM array for each UPM is 64 locations deep and 32 bits wide, as shown in Figure 15-38. The signals at the bottom of Figure 15-38 are UPM outputs. The selected CS is for the bank that matches the current address.
Page 464 User-Programmable Machines (UPMs) 10 11 Field CST4 CST1 CST2 CST3 BST4 BST1 BST2 BST3 G1T4 G1T3 G2T4 G2T3 Reset — Addr MCR[MAD] indirect addressing of 1 of 64 entries 26 27 Field G3T4 G3T3 G4T4/ G4T3/ G5T4 G5T3 — LOOP EXEN UTA TODT LAST DLT3 W AEN...
Page 465 User-Programmable Machines (UPMs) Table 15-14. RAM Word Bit Settings (Continued) Name Description BST3 Byte-select timing 3. Deﬁnes the state of BS during clock phase 4. 0 Asserted at the falling edge of GCLK1_50. 1 Negated at the falling edge of GCLK1_50. The ﬁnal value of the BS lines depends on the values of BRx[PS], the TSIZ lines, and A[30–31] for the access.
Page 466 User-Programmable Machines (UPMs) Table 15-14. RAM Word Bit Settings (Continued) Name Description G4T3/ General-purpose line 4 timing 3/wait enable. Function depends on the value of MxMR[GPLx4DIS]. W AEN G4T3 If MxMR[GPLx4DIS] = 0, G4T3 is selected. 0 The value of GPL4 at the falling edge of GCLK1_50 will be 0. 1 The value of GPL4 at the falling edge of GCLK1_50 will be 1.
Page 467 User-Programmable Machines (UPMs) Table 15-14. RAM Word Bit Settings (Continued) Name Description UPM transfer acknowledge. Controls the state of TA sampled by the external bus interface in the current memory cycle. TA is output at the rising edge of GCLK2_50. 0 TA is driven low on the rising edge of GCLK2_50.
Page 468 User-Programmable Machines (UPMs) 15.6.4.3 Byte-Select Signals (BST x ) BRx[MS] of the accessed memory bank selects a UPM on the currently requested cycle. The selected UPM affects only the assertion and negation of the appropriate BS signal; its timing as speciÞed in the RAM word. The state of each BS[0Ð3] signal depends on the value of each BSTx bit and the values of BRx[PS], TSIZn, and A[30Ð31] in the current cycle.The BS signals are also controlled by the port size of the accessed bank, the transfer size of the transaction, and the address accessed.
Page 469 User-Programmable Machines (UPMs) 15.6.4.4 General-Purpose Signals (G x T x , G0 x ) The general-purpose signals (GPL[1Ð5]) have two bits in the RAM word that deÞne the logical value of the signal to be changed at the falling edge of GCLK1_50 or GCLK2_50. GPL0 has two 2-bit Þelds that perform this function plus an additional function explained below.
Page 470 User-Programmable Machines (UPMs) Table 15-16. GPL_X5 Signal Behavior OR x Controlling Machine RAM Word GPL_X5 Behavior at the Controlling Clock Edge Memory Slave Access G5LA G5LS G5T4 G5T3 Access Clock Cycle GPCM GPL_A5 and GPL_B5 do not change their value. UPMA First GPL_A5 is driven low at the falling edge of GCLK1_50.
Page 471 User-Programmable Machines (UPMs) Continued loop execution depends on the loop counter. If the counter is not zero, the next RAM word executed is the loop start word. Otherwise, the next RAM word executed is the one after the loop end word. Loops can be executed sequentially but cannot be nested. Table 15-17.
Page 472 User-Programmable Machines (UPMs) The AMX Þeld can be used to output the contents of MAR on the address signals. Figure 15-43 shows address multiplex timing. CLKOUT/ GCLK2_50 GCLK1_50 A[0–31] Address Controlled by SAM Address Controlled by AMx of previous RAM word RAM Word 1 RAM Word 2 Figure 15-43.
Page 473 User-Programmable Machines (UPMs) Table 15-19 shows how AMx can be deÞned to interface with a range of DRAM modules. Table 15-19. AMA/AMB Definition for DRAM Interface DRAM Address Pin Number Data Bus MPC857T Address AM x Memory Size Width Pin Connection Column 8 bits 64 Kbyte...
Page 474 User-Programmable Machines (UPMs) Table 15-19. AMA/AMB Definition for DRAM Interface (Continued) DRAM Address Pin Number Data Bus MPC857T Address Memory Size AM x Width Pin Connection Column 8 bits 1 Mbyte A22–A31 2 Mbyte A21–A31 4 Mbyte A20–A31 8 Mbyte A19–A31 16 Mbyte A18–A31...
Page 475 User-Programmable Machines (UPMs) Table 15-19. AMA/AMB Definition for DRAM Interface (Continued) DRAM Address Pin Number Data Bus MPC857T Address Memory Size AM x Width Pin Connection Column 16 bits 128 Kbyte A23–A30 256 Kbyte A22–A30 512 Kbyte A21–A30 1 Mbyte A20–A30 2 Mbyte A19–A30...
Page 476 User-Programmable Machines (UPMs) Table 15-19. AMA/AMB Definition for DRAM Interface (Continued) DRAM Address Pin Number Data Bus MPC857T Address Memory Size AM x Width Pin Connection Column 32 bits 256 Kbyte A22–A29 512 Kbyte A21–A29 1 Mbyte A20–A29 2 Mbyte A19–A29 4 Mbyte A18–A29...
Page 477 User-Programmable Machines (UPMs) ¥ If G4T4/DLT3 functions as DLT3 and DLT3 = 1 in the RAM word, data is latched on the falling edge of GCLK2_50 instead of the rising edge, which is normal. This feature lets the user speed up the memory interface by latching data 1/2 clock early, which can be useful during burst reads.
Page 478 User-Programmable Machines (UPMs) 15.6.4.11.1 Internal and External Synchronous Masters If the UPM reads a RAM word with the WAEN bit set, the external UPWAIT signal is sampled and synchronized by the memory controller and the current request is frozen (if and while UPWAIT remains asserted).
Page 479 Handling Devices with Slow or Variable Access Times state until AS is negated. This allows TA to be used as an asynchronous handshake signal by programming UTA = 0 in the same RAM word in which WAEN = 1. If this is done, TA can be used to signal that AS should deassert (similar to DTACK in the 68000 bus).
Page 480 External Master Support ¥ The external TA mechanism is used only in accesses controlled by the GPCM. ORx[SETA] speciÞes whether TA is generated internally or externally. The following sections show how the two mechanisms work. 15.7.1 Hierarchical Bus Interface Example Assume that the CPU initiates a local-bus read cycle that addresses main memory connected to the system bus.
Page 481 External Master Support 15.8.1 Synchronous External Masters Synchronous masters initiate a transfer by asserting TS. A[0Ð31], RD/WR, BURST, and TSIZ must be stable before the rising edge of CLKOUT after TS is asserted and until the last TA is negated. Because the external master operates synchronously with the MPC857T, meeting setup and hold times for all inputs associated with the rising edge of CLKOUT is critical.
Page 482 External Master Support latched by the memory controller and on subsequent clock cycles, BADDR[28Ð30] increments as programmed in the UPM. 15.8.4.2 Handshake Mechanism for Asynchronous External Masters A wait mechanism in the UPM supports handshaking for external asynchronous masters. This is provided with an AS input signal and the WAEN bit in the UPM RAM words. See Section 15.6.4.11, ÒThe Wait Mechanism (WAEN).Ó...
Page 483 External Master Support CLKOUT A[–27] A[28–31] BURST TSIZ Data Address Memory Match and Device Compare Access Figure 15-47. Synchronous External Master Access Chapter 15. Memory Controller 15-57...
Page 484 External Master Support CLKOUT A[–27] A[28–31] TSIZ Data Address Memory Match and Device Compare Access Figure 15-48. Asynchronous External Master Access 15.8.5.2 External Masters and the UPM Figure 15-49 shows a synchronous interconnection in which an external master and the MPC857T can share access to a DRAM bank.
Page 485 External Master Support DRAM BS[0–3] Bank GPL_A5 Multiplexer BADDR[28–30] A[0–31] D[0–31] BURST External MPC8657T Master TSIZ[0–1] Figure 15-49. Synchronous External Master Interconnect Example Chapter 15. Memory Controller 15-59...
Page 486 External Master Support CLKOUT GCLK1 A[–31] BURST D[0–31] CS1 (RAS) BS[0–3] (CAS[0–3]) A[28–29] L/4 + 1 Mod 4 L/4 + 2 Mod 4 L/4 + 3 Mod 4 GPL5 cst4 Bit 0 cst1 Bit 1 cst2 Bit 2 cst3 Bit 3 bst4 Bit 4 bst1...
Page 487 External Master Support Figure 15-51 shows an asynchronous interconnection in which an external master and the MPC857T can share access to a DRAM bank. Notice that CS1, UPMA, and GPL_A5 were chosen to control DRAM bank accesses. Figure 15-52 shows the timing behavior of GPL_A5 and other control signals when an external master to a DRAM bank initiates a single-beat read.
Page 488 External Master Support CLKOUT/GCLK2_50 GCLK1_50 A[–31] D[0–31] CS1 (RAS) BS[0–3] (CAS[0–3]) GPL_A5 cst4 Bit 0 cst1 Bit 1 cst2 Bit 2 cst3 Bit 3 bst4 Bit 4 bst1 Bit 5 bst2 Bit 6 bst3 Bit 7 • • • • •...
Page 489 Memory System Interface Examples 15.9 Memory System Interface Examples The following examples show how to connect and set up the UPM RAM array for two types of DRAMÑpage mode DRAM and page mode extended data-out DRAM. The values used in these examples apply to any UPM. UPMA is used in the page mode example and UPMB is used in the extended data out example.
Page 490 Memory System Interface Examples 3. Translate the timing diagrams into RAM words for each type of memory access. The bottom half of the Þgures represent the RAM array contents that handle each of the possible cycles and each column represents a different word in the RAM array. A blank cell in the Þgures indicates a donÕt care bit, which is typically programmed to logic 1 to conserve power.
Page 491 Memory System Interface Examples CLKOUT/GCLK2_50 GCLK1_50 A[–31] Column D[0–31] CS1 (RAS) BS_A[0–3] (CAS[0–3]) cst4 Bit 0 cst1 Bit 1 cst2 Bit 2 cst3 Bit 3 bst4 Bit 4 bst1 Bit 5 bst2 Bit 6 bst3 Bit 7 g0l0 Bit 8 g0l1 Bit 9 g0h0...
Page 492 Memory System Interface Examples CLKOUT/GCLK2_50 GCLK1_50 A[–31] Column D[0–31] CS1 (RAS) BS_A[0–3] (CAS[0–3]) cst4 Bit 0 cst1 Bit 1 cst2 Bit 2 cst3 Bit 3 bst4 Bit 4 bst1 Bit 5 bst2 Bit 6 bst3 Bit 7 g0l0 Bit 8 g0l1 Bit 9 g0h0...
Page 493 Memory System Interface Examples CLKOUT/GCLK2_50 GCLK1_50 A[–31] Column 1 Column 2 Column 3 Column 4 D[0–31] CS1 (RAS) BS_A[0–3] (CAS[0–3]) cst4 Bit 0 cst1 Bit 1 cst2 Bit 2 cst3 Bit 3 bst4 Bit 4 bst1 Bit 5 bst2 Bit 6 bst3 Bit 7 g0l0...
Page 494 Memory System Interface Examples CLKOUT/GCLK2_50 GCLK1_50 A[–31] Column 1 Column 2 Column 3 Column 4 D[0–31] CS1 (RAS) BS_A[0–3] (CAS[0–3]) cst4 Bit 0 cst1 Bit 1 cst2 Bit 2 cst3 Bit 3 bst4 Bit 4 bst1 Bit 5 bst2 Bit 6 bst3 Bit 7 g0l0...
Page 495 Memory System Interface Examples CLKOUT/GCLK2_50 GCLK1_50 A[–31] Column 1 Column 2 Column 3 Column 4 D[0–31] CS1 (RAS) BS_A[0–3] (CAS[0–3]) cst4 Bit 0 cst1 Bit 1 cst2 Bit 2 cst3 Bit 3 bst4 Bit 4 bst1 Bit 5 bst2 Bit 6 bst3 Bit 7 g0l0...
Page 496 Memory System Interface Examples CLKOUT/GCLK2_50 GCLK1_50 A[–31] Column 1 Column 2 Column 3 Column 4 D[0–31] CS1 (RAS) BS_A[0–3] (CAS[0–3]) cst4 Bit 0 cst1 Bit 1 cst2 Bit 2 cst3 Bit 3 bst4 Bit 4 bst1 Bit 5 bst2 Bit 6 bst3 Bit 7 g0l0...
Page 497 Memory System Interface Examples CLKOUT/GCLK2_50 GCLK1_50 CS1 (RAS) BS_A[0–3] (CAS[0–3]) cst4 Bit 0 cst1 Bit 1 cst2 Bit 2 cst3 Bit 3 bst4 Bit 4 bst1 Bit 5 bst2 Bit 6 bst3 Bit 7 g0l0 Bit 8 g0l1 Bit 9 g0h0 Bit 10 g0h1...
Page 498 Memory System Interface Examples CLKOUT/GCLK2_50 GCLK1_50 CS1 (RAS) BS_A[0–3] (CAS[0–3]) cst4 Bit 0 cst1 Bit 1 cst2 Bit 2 cst3 Bit 3 bst4 Bit 4 bst1 Bit 5 bst2 Bit 6 bst3 Bit 7 g0l0 Bit 8 g0l1 Bit 9 g0h0 Bit 10 g0h1...
Page 499 Memory System Interface Examples CLKOUT/GCLK2_50 GCLK1_50 A[–31] Col 1 Col 2 Col 3 Col 4 D[0–31] CS1 (RAS) BS_A[0–3] (CAS[0–3]) cst4 Bit 0 cst1 Bit 1 cst2 Bit 2 cst3 Bit 3 bst4 Bit 4 bst1 Bit 5 bst2 Bit 6 bst3 Bit 7 g0l0...
Page 500 Memory System Interface Examples 15.9.2 Page Mode Extended Data-Out Interface Example Figure 15-63 shows the conÞguration for a 1-Mbyte, 32-bit wide memory system using two 256K x 16-bit page mode EDO DRAMs. Also shown is the physical connection between UPMB and the EDO DRAMs. The CS2 signal controlled by BRx is connected to both RAS signals.
Page 501 Memory System Interface Examples 4. DeÞne the UPMB (or UPMA) parameters that control the memory system in the following sequence. For additional details, see Table 15-20. Ñ Program the RAM array using MCR and MDR. The RAM word must be written into the MDR before a command is issued to the MCR.
Page 502 Memory System Interface Examples CLKOUT/GCLK2_50 GCLK1_50 A[0–31] Column D[0–31] CS2 (RAS) BS_B[0–3] (CAS[0–3]) GPL_B1 (OE) cst4 Bit 0 cst1 Bit 1 cst2 Bit 2 cst3 Bit 3 bst4 Bit 4 bst1 Bit 5 bst2 Bit 6 bst3 Bit 7 g0l0 Bit 8 g0l1 Bit 9...
Page 503 Memory System Interface Examples CLKOUT/GCLK2_50 GCLK1_50 A[0–31] Column D[0–31] CS2 (RAS) BS_B[0–3] (CAS[0–3]) GPL_B1 (OE) cst4 Bit 0 cst1 Bit 1 cst2 Bit 2 cst3 Bit 3 bst4 Bit 4 bst1 Bit 5 bst2 Bit 6 bst3 Bit 7 g0l0 Bit 8 g0l1 Bit 9...
Page 504 Memory System Interface Examples CLKOUT/GCLK2_50 GCLK1_50 A[0–31] Column 1 Column 2 Column 3 Column 4 D[0–31] CS2 (RAS) BS_B[0–3] (CAS[0–3]) GPL_B1 (OE) cst4 Bit 0 cst1 Bit 1 cst2 Bit 2 cst3 Bit 3 bst4 Bit 4 bst1 Bit 5 bst2 Bit 6 bst3...
Page 505 Memory System Interface Examples CLKOUT/GCLK2_50 GCLK1_50 A[0–31] Column 1 Column 2 Column 3 Column 4 D[0–31] CS2 (RAS) BS_B[0–3] (CAS[0–3]) GPL_B1 (OE) cst4 Bit 0 cst1 Bit 1 cst2 Bit 2 cst3 Bit 3 bst4 Bit 4 bst1 Bit 5 bst2 Bit 6 bst3...
Page 506 Memory System Interface Examples CLKOUT/GCLK2_50 GCLK1_50 CS2 (RAS) BS_B[0–3] (CAS[0–3]) GPL_B1 (OE) cst4 Bit 0 cst1 Bit 1 cst2 Bit 2 cst3 Bit 3 bst4 Bit 4 bst1 Bit 5 bst2 Bit 6 bst3 Bit 7 g0l0 Bit 8 g0l1 Bit 9 g0h0 Bit 10...
Page 507 Memory System Interface Examples CLKOUT/GCLK2_50 GCLK1_50 CS2 (RAS) BS_B[0–3] (CAS[0–3]) GPL_B1 (OE) cst4 Bit 0 cst1 Bit 1 cst2 Bit 2 cst3 Bit 3 bst4 Bit 4 bst1 Bit 5 bst2 Bit 6 bst3 Bit 7 g0l0 Bit 8 g0l1 Bit 9 g0h0 Bit 10...
Page 508 Memory System Interface Examples CLKOUT/GCLK2_50 GCLK1_50 A[–31] D[0–31] CSx (RAS) BS_x[0–3] (CAS[0–3]) GPL_x1 (OE) cst4 Bit 0 cst1 Bit 1 cst2 Bit 2 cst3 Bit 3 bst4 Bit 4 bst1 Bit 5 bst2 Bit 6 bst3 Bit 7 g0l0 Bit 8 g0l1 Bit 9 g0h0...
Page 509 Chapter 16 PCMCIA Interface The PCMCIA host adapter module provides all control logic for a PCMCIA socket interface, and requires only additional external analog power switching logic and buffering. Additional external buffers allow the PCMCIA host adapter module to support up to two PCMCIA sockets.
Page 510 PCMCIA Module Signal Deﬁnitions Socket Power-On Indication V CC _A V PP 1_A MAX 780A PCMCIA or Equivalent Host V PP 2_A Adapter Module 5 V 12 V Transceiver Data_A[8–15] D[8–15] Data_A[0–7] D[0–7] RD/WR Buffer with OE CE1_A/B CE1_A CE2_A/B CE2_A WE/PGM_A WE/PGM...
Page 511 PCMCIA Module Signal Deﬁnitions 16.2.1 PCMCIA Cycle Control Signals Table 16-1 describes PCMCIA cycle control signals. Table 16-1. PCMCIA Cycle Control Signals Signal Description A[6–31] Address bus. Output. A[6–31] should be buffered to generate the socket signals A[25–0]. These address bus output lines allow direct addressing of 64 Mbytes of memory on each PCMCIA card.
Page 512 PCMCIA Module Signal Deﬁnitions 16.2.2 PCMCIA Input Port Signals The following signals are used by a PCMCIA slot to indicate card status. The MPC857T provides synchronization, transition detection, optional interrupt generation, and the means for the software to read the signal state. This function is not necessarily speciÞc to PCMCIA;...
Page 513 Operation Description 16.2.3 PCMCIA Output Port Signals (OP[0–4]) A PCMCIA slot can use the signals in Table 16-3 to control the RESET input and output enable of the buffers to the card. The MPC857T gives software a way to control the output signal state.
Page 514 Operation Description Table 16-5. Host Programming for Memory Cards 600 ns 200 ns 150 ns 100 ns Memory Access Time Clock Cycle 20 ns (50 MHz) 30 ns (33.3 MHz) 40 ns (25 MHz) 62 ns (16 MHz) 83 ns (12 MHz) Because the minimum hold time is one clock, the real access time is access time + one clock.
Page 515 Operation Description 16.3.4 Power Control The user can perform a write cycle using one of the memory controller chip-select pins. This data includes the controls to the analog switch such as the MAXIM MAX780. However, no auto-power control is supported. 16.3.5 Reset and Three-State Control The user can reset the PCMCIA cards or disable the output of the external latches by writing to PGCRx[CxRESET] and PGCRx[CxOE], respectively.
Page 516 Programming Model 16.4 Programming Model This section describes the PCMCIA interface programming model. Generally, all registers are memory-mapped within the internal control register area. The registers in Table 16-7 control the PCMCIA interface. Table 16-7. PCMCIA Registers Name Description PIPR PCMCIA interface input pins register PSCR PCMCIA interface status changed register...
Page 517 Programming Model Table 16-8 describes PIPR Þelds. Table 16-8. PIPR Field Descriptions Bits Name Description 8–15 — Reserved, should be cleared. CBVS1 Voltage sense 1 for card B CBVS2 Voltage sense 2 for card B CBWP Write protect for card B CBCD2 Card detect 2 for card B CBCD1...
Page 518 Programming Model Table 16-9. PSCR Field Descriptions (Continued) Bits Name Description CBCD2_C Card detect 2 for card B changed CBCD1_C Card detect 1 for card B changed CBBVD2_C Battery voltage/SPKR_B input for card B changed CBBVD1_C Battery voltage/STSCHG_B input for card B changed —...
Page 519 Programming Model Table 16-10. PER Field Descriptions (Continued) Bits Name Description CB_ECD2 Enable for card detect 2 for card B changed. Setting this bit enables the interrupt on any signal change. CB_ECD1 Enable for card detect 1 for card B changed. Setting this bit enables the interrupt on any signal change.
Page 520 Programming Model Table 16-11. PGCRx Field Descriptions (Continued) Bits Name Description 16–17 CxDREQ Card x DREQ. Deﬁnes internal DMA request for the on-chip DMA controller (CADREQ controls DMA channel 0. CBDREQ controls DMA channel 1). 0x Disable internal DMA request from slot x. 10 Enable IOIS16_x as internal DMA request for slot x.
Page 521 Programming Model Field BSIZE — PSHT Reset Undeﬁned Addr (IMMR & 0xFFFF0000) + 0x084 (POR0); 0x08C (POR1); 0x094 (POR2); 0x09C (POR3); 0x0A4 (POR4); 0x0AC (POR5); 0x0B4 (POR6); 0x0BC (POR7) Field PSST PSLOT Reset Undeﬁned Addr (IMMR & 0xFFFF0000) + 0x086 (POR0); 0x08E (POR1); 0x096 (POR2); 0x09E (POR3); 0x0A6 (POR4); 0x0AE (POR5);...
Page 522 Programming Model Table 16-13. POR Field Descriptions (Continued) Bits Name Description 0–4 BSIZE (cont.) BSIZE determines not only the bank size, but also how the address is compared with PBRB[PBA]. If virtual ﬁeld, MASK, is deﬁned as shown below: BSIZE MASK 00000 1111 1111 1111 1111 1111 1111 1111 1111...
Page 523 Programming Model Table 16-13. POR Field Descriptions (Continued) Bits Name Description 20–24 PCMCIA strobe length. Determines the number of cycles the strobe is asserted during a PCMCIA access for this window and, thus, it is the main parameter for determining cycle length. The cycle may be lengthened by asserting WAIT.
Page 524 PCMCIA Controller Timing Examples 16.5 PCMCIA Controller Timing Examples CLKOUT A[6–31] RD/WR BURST CE1/CE2 PCOE WAIT Data PSST PSHT Figure 16-9. PCMCIA Single-Beat Read Cycle PRS = 0 PSST = 1 PSL = 3 PSHT = 1 16-16 MPC857T PowerQUICC User’s Manual...
Page 525 PCMCIA Controller Timing Examples CLKOUT A[6–31] RD/WR BURST CE1/CE2 PCOE WAIT Data PSST PSHT Figure 16-10. PCMCIA Single-Beat Read Cycle PRS = 0 PSST = 2 PSL = 4 PSHT = 1 Chapter 16. PCMCIA Interface 16-17...
Page 526 PCMCIA Controller Timing Examples CLKOUT A[6–31] RD/WR BURST CE1/CE2 PCOE WAIT Data PSHT PSST Figure 16-11. PCMCIA Single-Beat Read Cycle PRS = 0 PSST = 1 PSL = 3 PSHT = 0 16-18 MPC857T PowerQUICC User’s Manual...
Page 527 PCMCIA Controller Timing Examples CLKOUT A[6–31] RD/WR BURST CE1/CE2 PCWE WAIT Data PSST PSHT Figure 16-12. PCMCIA Single-Beat Write Cycle PRS = 2 PSST = 1 PSL = 3 PSHT = 1 Chapter 16. PCMCIA Interface 16-19...
Page 528 PCMCIA Controller Timing Examples CLKOUT A[6–31] RD/WR BURST CE1/CE2 IOWR WAIT Data IO16 PSST PSHT Figure 16-13. PCMCIA Single-Beat Write Cycle PRS = 3 PSST = 1 PSL = 4 PSHT = 3 16-20 MPC857T PowerQUICC User’s Manual...
Page 529 PCMCIA Controller Timing Examples CLKOUT A[6–31] RD/WR BURST CE1/CE2 IOWR WAIT Data PSHT PSST Wait Delay Figure 16-14. PCMCIA Single-Beat Write with Wait PRS = 3 PSST = 1 PSL = 3 PSHT = 0 Chapter 16. PCMCIA Interface 16-21...
Page 530 PCMCIA Controller Timing Examples CLKOUT A[6–31] RD/WR BURST CE1/CE2 IORD WAIT Data PSST Wait Delay PSHT Figure 16-15. PCMCIA Single-Beat Read with Wait PRS = 3 PSST = 1 PSL = 3 PSHT =1 16-22 MPC857T PowerQUICC User’s Manual...
Page 531 PCMCIA Controller Timing Examples CLKOUT A[6–31] RD/WR BURST IOWR Data IO16 PSHT PSST Figure 16-16. PCMCIA I/O Read PPS = 1 PRS = 3 PSST = 1 PSL = 2 PSHT = 0 Chapter 16. PCMCIA Interface 16-23...
Page 532 PCMCIA Controller Timing Examples CLKOUT A[6–31] RD/WR BURST IOWR Data IO16 PSHT PSHT PSST PSST Figure 16-17. PCMCIA I/O Read PPS = 1 PRS = 3 PSST = 1 PSL = 2 PSHT = 0 16-24 MPC857T PowerQUICC User’s Manual...
Page 533 PCMCIA Controller Timing Examples CLKOUT A[6–31] AT = 0xF AT = 0xF RD/WR BURST CE1/CE2 IORD PCOE SIZE SIZE = Word SIZE = Half Data PSHT PSHT PSST PSST Figure 16-18. PCMCIA DMA Read Cycle PRS = 4 PSST = 1 PSL = 3 PSHT = 0 Chapter 16.
Page 534 PCMCIA Controller Timing Examples 16-26 MPC857T PowerQUICC User’s Manual...
Page 535 Part V Communications Processor Module Intended Audience Part V is intended for system designers who need to implement various communications protocols on the MPC857T. It assumes a basic understanding of the PowerPC exception model, the MPC857T interrupt structure, as well as a working knowledge of the communications protocols to be used.
Page 536 ¥ Chapter 22, ÒSCC UART Mode,Ó describes the MPC857T implementation of universal asynchronous receiver transmitter (UART) protocol, used for sending low-speed data between devices. ¥ Chapter 23, ÒSCC HDLC Mode,Ó describes the MPC857T implementation of HDLC protocol. ¥ Chapter 24, ÒSCC AppleTalk Mode,Ó describes the MPC857T implementation of AppleTalk, a set of protocols developed by Apple Computer, Inc.
Page 537 ¥ Chapter 34, ÒCPM Interrupt Controller,Ó describes how the CPM interrupt controller (CPIC) accepts and prioritizes the internal and external interrupt requests from the CPM blocks and passes them to the system interface unit (SIU). The CPIC also provides a vector during the core interrupt acknowledge cycle. Suggested Reading This section lists additional reading that provides background for the information in this manual as well as general information about the PowerPC architecture.
Page 538 Conventions This document uses the following notational conventions: Bold entries in Þgures and tables showing registers and parameter Bold RAM should be initialized by the user. Instruction mnemonics are shown in lowercase bold. mnemonics Italics indicate variable command parameters, for example, bcctrx. italics Book titles in text are set in italics.
Page 539 Table vi. Acronyms and Abbreviated Terms (Continued) Term Meaning Condition/indication channel used in the GCI protocol Communications processor Communications processor module Direct memory access DPLL Digital phase-locked loop DRAM Dynamic random access memory DSISR Register used for determining the source of a DSI exception Effective address EEST Enhanced Ethernet serial transceiver...
Page 540 Table vi. Acronyms and Abbreviated Terms (Continued) Term Meaning Pulse-position modulation RTOS Real-time operating system Receive Serial communications controller Serial control port SDLC Synchronous Data Link Control SDMA Serial DMA Serial interface System interface unit Serial management controller Systems network architecture Serial peripheral interface SRAM Static random access memory...
Page 541 Chapter 17 Communications Processor Module and CPM Timers The communications processor module (CPM) provides a ßexible and integrated approach to communications-intensive environments. To reduce system frequency and save power, the CPM has its own independent RISC communications processor (CP) that is optimized for serial communications.
Page 542 Features 17.1 Features Figure 17-1 shows a block diagram of the CPM. U-Bus Interrupt Controller Bus Interface SDMA Internal Bus 4 Timers Communications Processor Dual-Port Parallel I/O Ports 4 Baud Rate Generators Peripheral Bus SCC1 SCC3 SCC4 SMC1 SMC2 Serial Interface and Time-Slot Assigner Figure 17-1.
Page 543 Features ¥ A full-duplex serial communications controller (SCC1) that supports the following: Ñ UART protocol (asynchronous or synchronous) Ñ HDLC protocol Ñ AppleTalk protocol Ñ Asynchronous HDLC protocol Ñ BISYNC protocol Ñ Transparent protocol Ñ Infrared protocol (IrDA) Ñ IEEE802.3/Ethernet protocol ¥...
Page 544 CPM General-Purpose Timers supports various communications links and protocols. MPC857T RJ-45 EEST SCC1 MC68160 D-15 Passive Embedded 8-Bit Boot PowerPC EPROM Core 32-Bit RISC DRAM SIMM Communications 16- or 32-Bit Processor (Parity Optional) TDMa T1/E1 T1/E1 Line Xceiver Time-Slot CA91C860 Assigner PCI Bus QSPAN-860...
Page 545 CPM General-Purpose Timers Figure 17-3 is a block diagram of the CPM timers. General System Clock TGCR Global Configuration Register TGATE1 TER1 Timer Event Register TGATE2 Clock Generator TIN1 Mode Register TMR1 Prescaler Mode Bits TIN2 TIN3 Divider Clock TIN4 TCN1 Timer Counter (TCN) Capture...
Page 546 CPM General-Purpose Timers 17.2.2 CPM Timer Operation The following subsections describe the timer operation. The timer mode registers (TMRx) and the timer global conÞguration register (TGCR) mentioned in this section are described in Section 17.2.3, ÒCPM Timer Register Set.Ó 17.2.2.1 Timer Clock Source The clock input to the prescaler can be selected from three sources: ¥...
Page 547 CPM General-Purpose Timers 17.2.2.4 Timer Gating Timers can be gated or restarted by one of two external gate signalsÑTGATE1for timer 1 and/or 2, TGATE2 for timer 3 and/or 4. Normal gate mode enables the count on a falling edge of TGATEx and disables the count on the rising edge of TGATEx. This allows the timer to count conditionally, depending on the state of TGATEx.
Page 548 CPM General-Purpose Timers 17.2.2.6 Timer 1 and SPKROUT Timer 1 can be used to drive audio alerts through the PCMCIA SPKROUT signal. Enabling timer 1 results in SPKROUT being driven with timer 1's frequency. Timer 1 is exclusive ORed with the resulting exclusive OR of the SPKR_A and SPKR_B input signals to generate SPKROUT.
Page 549 CPM General-Purpose Timers Table 17-1. TGCR Field Descriptions (Continued) Bits Name Description Gate mode for TGATE2. Valid only if TMR3[GE] or TMR4[GE] is set. 0 Restart gate mode. A falling edge of TGATE2 enables and restarts the count and a rising edge of TGATE2 disables the count.
Page 550 CPM General-Purpose Timers Table 17-2. TMR1–TMR4 Field Descriptions (Continued) Bits Name Description Free run/restart. 0 Free run. The timer count continues to increment after the reference value is reached. 1 Restart. The timer count is reset immediately after the reference value is reached. 13–14 ICLK Input clock source for the timer.
Page 551 CPM General-Purpose Timers 17.2.4.3 Timer Counter Registers (TCN1–TCN4) Each timer counter register (TCN1ÐTCN4), shown in Figure 17-9, is an up-counter. A read cycle to TCN1ÐTCN4 yields the current value of the timer, but does not affect the counting operation. A write cycle to TCN1ÐTCN4 sets the register to the written value, thus causing its corresponding prescaler, TMRx[PS], to be reset.
Page 552 CPM General-Purpose Timers 17.2.5 Timer Initialization Examples The following two initialization sequences program timer 2 to generate an interrupt every 10 µs. The Þrst sequence uses timer 2 alone, while the second example uses timers 1 and 2 in cascaded mode. Assuming a 25-MHz general system clock, an interrupt should be generated every 250 system clocks.
Page 553 Chapter 18 Communications Processor Transacting with the communications peripherals on a separate bus from the PowerPC core, the CPMÕs 32-bit communications processor (CP) handles the low-level communications tasks, freeing the core for higher-level tasks. The CP implements the chosen protocols using the serial controllers and parallel interface port and manages the data transfer through the serial DMA (SDMA) channels between the I/O channels and memory.
Page 554 Communicating with the Core Figure 18-1 is a block diagram of the CP. INSTRUCTION STORAGE PROCESSING UNITS Multiplier/ Decoder Accumulator Register Cyclic Peripheral File Redundancy • Interface Development Check • Sequencer Support • Arithmetic Logic Unit Scheduler Peripheral Dual-Port Service Requests Figure 18-1.
Page 555 CP Microcode Revision Number Table 18-1 shows the order in which the CP handles requests from peripherals from highest to lowest priority. Table 18-1. Peripheral Prioritization Priority Request Reset in the CPCR or SRESET SDMA bus error Commands issued to the CPCR IDMA emulation: DREQ0 (default—option 1) IDMA emulation: DREQ1 (default—option 1) SCC1 Rx...
Page 556 CP Register Set and CP Commands Table 18-2. CP Microcode Revision Number Offset Name Width Description 0x00 REV_NUM Half-word Microcode revision number 0x02 — Half-word Reserved 0x04 — Word Reserved 0x08 — Word Reserved Offset from the base of the miscellaneous parameter area (at offset 0x1CB0 of the dual-port RAM). For the latest documentation on part/revision numbers and microcode REV_NUMs, see the website at http://www.motorola.com/SPS/RISC/netcomm/.
Page 557 CP Register Set and CP Commands Table 18-3. RCCR Field Descriptions (Continued) Bits Name Description DR1M IDMA request 1 mode. Controls the IDMA request 1 (DREQ1) sensitivity mode. See Section 19.3.7, “IDMA Interface Signals—DREQ and SDACK.” 0 DREQ1 is edge-sensitive. 1 DREQ1 is level-sensitive.
Page 558 CP Register Set and CP Commands RMDS Þelds are described in Table 18-4. Table 18-4. RMDS Field Descriptions Bits Name Description ERAM4K Enable RAM microcode (at offset 4K) 0 Microcode may be executed only from the ﬁrst 2 Kbytes of the dual-port RAM. 1 Microcode is also executed from the 2 Kbytes of the second half of the dual-port RAM with a 512-byte extension.
Page 559 CP Register Set and CP Commands Table 18-5. CPCR Field Descriptions (Continued) Bits Name Description 8–11 CH_NUM Channel number. Deﬁnes the speciﬁc sub-block on which the command is to operate. Some sub-blocks share channel number encodings if their commands are mutually exclusive. 0000 SCC1 0001 I C/IDMA1...
Page 560 Dual-Port RAM Table 18-6. CP Commands (Continued) Command Description Stop IDMA transfers. The CP terminates current IDMA transfers. STOP IDMA Used to activate, deactivate, or reconﬁgure the 16 timers of the RISC timer table. SET TIMER Sets a hash table bit for the Ethernet logical group address recognition function. SET GROUP ADDRESS GCI receiver sends an abort request.
Page 561 Dual-Port RAM Dual-Port RAM 1,024 Bytes BD/Buffers/Microcode 1,024 Bytes BD/Buffers/Microcode 512 Bytes BD/Buffers/Microcode U-Bus Addr CP Microcode Instr Address 1,024 Bytes Data CP Microcode Instr Addr U-Bus Data BD/Buffers/Microcode Selectors Selectors CP Data Addr CP Data 1,024 Bytes BD/Buffers/Microcode 512 Bytes BD/Buffers/Microcode 2,048 Bytes BD/Buffers...
Page 562 Dual-Port RAM Figure 18-6. Dual-Port RAM Memory Map Kbyte– IMMR + 0x2000 ERAM = ERAM = ERAM = 01– BD/Data/Microcode 11– 10– IMMR + 0x2200 BD/Data/Microcode Kbyte– IMMR + 0x2400 BD/Data/Microcode Kbyte– IMMR + 0x2800 BD/Data Kbyte– IMMR + 0x2E00 ERAM = BD/Data/Microcode ERAM = 01,...
Page 563 Dual-Port RAM In addition to RCCR[ERAM], RMDS[ERAM4K] (enable RAM microcode at offset 4K) affects the system RAM memory conÞguration for microcode packages. Setting RMDS[ERAM4K] locks a 2-Kbyte block and a 512-byte extension (the lighter-shaded areas of Figure 18-6) for microcode execution. 18.6.2 The Buffer Descriptor (BD) The SCC, SMCs, SPI, IDMA, PIP, and I C use buffer descriptors (BDs) to deÞne the...
Page 564 The RISC Timer Table The SPI and I C parameter RAM areas can be relocated to other 32-byte aligned parameter areas in dual-port RAM by programming their 16-bit base offsets, shown in Table 18-9. Table 18-9. I C and SPI Parameter RAM Relocation Offset from DPRAM_base Size Controller/Peripheral...
Page 565 The RISC Timer Table behavior can be used to estimate the worst-case loading of the CP; see Section 18.7.8, ÒUsing the RISC Timers to Track CP Loading.Ó The timer table is conÞgured using the RCCR, the timer table parameter RAM, and the RISC controller timer event/mask registers (RTER/RTMR), and by issuing to the CPCR.
Page 566 The RISC Timer Table 16 RISC Timer Table Entries (Up to 64 Bytes) Timer Table Base Pointer DPRAM_BASE + 0x1DB0 TM_BASE RISC Timer Table Parameter RAM Figure 18-7. RISC Timer Table RAM Usage The RISC timer table parameter RAM holds the general timer parameters. Table 18-10 shows its memory map.
Page 567 The RISC Timer Table 18.7.3.1 RISC Timer Command Register (TM_CMD) Figure 18-8 shows the TM_CMD register. Field — Timer Number Field Timer Period Figure 18-8. RISC Timer Command Register (TM_CMD) Table 18-11 describes TM_CMD Þelds. Table 18-11. TM_CMD Field Descriptions Bits Name Description...
Page 568 The RISC Timer Table Field TMR1 TMR1 TMR1 TMR1 TMR1 TMR1 Reset 0000_0000_0000_0000 Addr 0x9D6 (RTER); 0x9DA (RTMR) Figure 18-9. RISC Timer Event Register (RTER)/Mask Register (RTMR) The RISC timer mask register (RTMR), also shown in Figure 18-9, is used to enable interrupts generated in the RTER.
Page 569 The RISC Timer Table 18.7.6 RISC Timer Initialization Follow these steps to initialize the RISC timers: 1. Program RCCR[TIMEP] to the preferred internal timer tick interval, which determines the scan interval for the entire timer table. The timer enable bit, RCCR[TIME], is normally set at this time;...
Page 570 The RISC Timer Table 8. Write 0x0851 to the CPCR to issue SET TIMER 9. Set RCCR[TIME] to start RISC timer table scanning. 18.7.7 RISC Timer Interrupt Handling The following sequence shows what normally occurs within an interrupt handler for the RISC timer table: 1.
Page 571 Chapter 19 SDMA Channels and IDMA Emulation The CPM controls two physical serial DMA (SDMA) channels on the MPC857T. Using the two physical channels, the CP implements ten virtual SDMA channels, each dedicated to a serial controller transmitter or receiverÑtwo for the full-duplex SCC, and the remaining eight for the SPI, I C, and the two SMCs.
Page 572 SDMA Channels 19.1.1 SDMA Transfers Each SDMA channel can be programmed to output a 3-bit function code that identiÞes the channel currently accessing memory. The SDMA channel can implement true little-endian, PowerPC little-endian, or big-endian byte ordering when accessing buffers. These features are programmed in the receive and transmit function code registers associated with each serial controller and within an IDMA channelÕs BD;...
Page 573 SDMA Registers Once an SDMA channel obtains the external system bus, it remains master for the whole transactionÑa byte, half-word, word or burst transferÑbefore relinquishing the bus. This feature, in combination with the zero-clock arbitration overhead provided by the U-bus, increases bus efÞciency and lowers latency.
Page 574 SDMA Registers Field — Reset 0000_0000_0000_0000 Addr IMMR + 0x030 Field — — RAID Reset 0000_0000_0000_0000 Addr IMMR + 0x032 Figure 19-3. SDMA Configuration Register (SDCR) Table 19-2 describes the SDCR bit settings. Table 19-2. SDCR Bit Settings Bits Name Description 0–16 —...
Page 575 IDMA Emulation Table 19-3 describes the SDSR bit settings. Table 19-3. SDSR Field Descriptions Bits Name Description SBER SDMA channel bus error. Indicates an error caused the SDMA channel to terminate during a read or write cycle. The SDMA bus error address can be retrieved from the SDMA address register (SDAR). 1–7 —...
Page 576 IDMA Emulation also remaps the IDMA1 channel parameter RAM. See Section 19.3.9, ÒSingle-Buffer Mode on IDMA1ÑA Special Case.Ó Note that DREQ0 is the DMA request for IDMA1, and DREQ1 is the DMA request for IDMA2. 19.3.1 IDMA Features The following is a list of IDMAÕs main features: ¥...
Page 577 IDMA Emulation Table 19-4. IDMA Parameter RAM Memory Map (Continued) 0x08 DAPR Word Destination data pointer (internal-use). Points to the next destination byte to be written. The CP initializes DAPR to the BD’s destination buffer pointer, and increments it automatically if the destination is memory (DCMR[S/D] = 0b0x). 0x0C IBPTR Hword...
Page 578 IDMA Emulation Table 19-5 describes DCMR Þelds. Table 19-5. DCMR Field Descriptions Bits Name Description 0–10 — Reserved. Should be cleared. 11–12 SIZE Peripheral port size. Determines the operand transfer size per DREQx assertion for peripheral/memory transfers, but not for memory/memory transfers. (For memory/memory transfers the size is determined only by address alignment and the amount of data remaining to be transferred.) 00 Word length.
Page 579 IDMA Emulation Table 19-6. IDSR1/IDSR2 Field Descriptions (Continued) Bits Name Description DONE Buffer chain done. Indicates IDMA transfer termination. Set after servicing a BD that has its L bit (last) set, regardless of the I bit setting. Out of buffers. Indicates that the IDMA channel has no valid BDs left in the BD table. 19.3.3.3 IDMA Mask Registers (IDMR1 and IDMR2) The read/write IDMA mask registers (IDMR1 and IDMR2) have the same format as IDSR, shown in Figure 19-6.
Page 580 IDMA Emulation ¥ The byte at (offset + 3) is the source function code register (SFCR). See Section 19.3.4.1, ÒFunction Code RegistersÑSFCR and DFCR.Ó ¥ The word at (offset + 4) is the buffer length, containing the number of bytes for transfer.
Page 581 IDMA Emulation Table 19-7. IDMA BD Status and Control Bits (Continued) Bits Name Description Interrupt. Enable the maskable auxiliary-done (AD) interrupt. 0 IDSR[AD] is not ﬂagged after this BD is processed. 1 IDSR[AD] is ﬂagged after this BD is processed. Last.
Page 582 IDMA Emulation 19.3.4.2 Auto-Buffering and Buffer-Chaining Buffer-chaining is designed to move large amounts of noncontiguous blocks of data. Even though each block needs a separate BD, the BDs can be chained together and serviced as a group. Auto-buffering is used to repeatedly service a BD chain. Note that a chain can range from one BD to the whole BD table in length.
Page 583 IDMA Emulation 19.3.6 IDMA Channel Operation An IDMA channel operation consists of the following eventsÑIDMA channel initialization, data transfer, and block termination. In the initialization phase, the core loads the global IDMA channel information into the IDMA parameter RAM, builds the IDMA BD table, and starts the channel.
Page 584 IDMA Emulation 19.3.7.1 IDMA Requests for Memory/Memory Transfers Because there is no internal mechanism, an externally-connected DREQ must still be used to generate IDMA memory/memory transfer requests. This can be done using a general-purpose I/O line or a general-purpose timer output. To use a general-purpose I/O line, follow these steps: 1.
Page 585 IDMA Emulation 19.3.7.2.2 Edge-Sensitive Requests Clearing RCCR[DRnM] makes the corresponding IDMA channel edge-sensitive to requests. The edge sensitivity is further qualiÞed to detect either any edge or falling edges only as programmed in PCINT[EDM15] and PCINT[EDM14] for DREQ0 and DREQ1, respectively;...
Page 586 IDMA Emulation source starting address, or destination starting address, IDMA uses the most efÞcient packing algorithm possible to perform the transfer in the least number of bus cycles. 19.3.8.2 Single-Address (Single-Cycle) Transfer (Fly-By) Each IDMA channel can be independently programmed to provide single-address, or ßy-by, transfers.
Page 587 IDMA Emulation CLKOUT Address SETUP HOLD Data SDACK DELAY PHOLD Figure 19-11. SDACK Timing Diagram: Single-Address Peripheral Write, Internally-Generated TA ¥ Single-address memory-write/peripheral-readÑThe source device is controlled by the IDMA handshake signals (DREQ and SDACK). When the source device requests service from the IDMA channel, IDMA asserts SDACK to allow the source device to drive data onto the data bus.
Page 588 IDMA Emulation CLKOUT Address Data SDACK HOLD DELAY Figure 19-12. SDACK Timing Diagram: Single-Address Peripheral Read, Internally-Generated TA 19.3.9 Single-Buffer Mode on IDMA1—A Special Case For single-buffer transfers from a peripheral to memory of up to 64 bytes per request, IDMA1 offers a reduced-latency solution using single-address bursts.
Page 589 IDMA Emulation 19.3.9.1 IDMA1 Channel Mode Register (DCMR) (Single-Buffer Mode) DCMR contains the channelÕs function code and byte-order convention, previously held in function code registers. DCMR also holds the channel start bit (enable) and burst transfer information. Figure 19-13 shows the DCMR format. Field —...
Page 590 IDMA Emulation Bits Field — DONE — Reset 0000_0000_0000_0000 Addr IMMR + 0x910 Figure 19-14. IDMA1 Status Register (IDSR1) (Single-Buffer Mode) 19.3.9.3 IDMA1 Mask Register (IDMR1) (Single-Buffer Mode) IDMR1 in single-buffer mode behaves the same way as deÞned above; see Section 19.3.3.3, ÒIDMA Mask Registers (IDMR1 and IDMR2).Ó...
Page 591 IDMA Emulation CLKOUT GCLK1 A[0:31] Column 1 Column 2 Column 3 Column 4 D[0:31] CS1 (RAS) BS[0:3] (CAS[0:3]) BDIP SDACK1 DREQ0 Figure 19-15. Single-Address IDMA1 Burst Timing (Single-Buffer Mode) 19.3.10 External Recognition of an IDMA Transfer The following are ways to externally determine if IDMA is executing a bus cycle: ¥...
Page 592 IDMA Emulation 19.3.11 Interrupts During an IDMA Bus Transfer The MPC857T supports a synchronous bus structure with provisions allowing a bus master to detect and respond to errors during a bus cycle. An IDMA channel recognizes the same bus interrupt sources that the core recognizesÑreset and transfer error acknowledge (TEA).
Page 593 Chapter 20 Serial Interface The physical interface to the SCC and SMCs is implemented in the serial interface (SI). The SI allows each individual SCC and SMC to be connected externally either through a time-division multiplexed (TDM) interface or through dedicated pins in a non-multiplexed serial interface (NMSI).
Page 594 Figure 20-1 shows the SI block diagram. U-Bus Tx / Rx Route Mode Command Status Clock SI RAM Register Register Register Route Control SMC1 SMC2 SCC1 Time-Slot Assigner TDM a TDM a SMC1 SMC2 SCC1 Strobes Pins Pins Pins Pins Non-multiplexed Serial Interface (NMSI) Figure 20-1.
Page 595 SI Features 20.1 SI Features The TSAÕs main features are as follows: ¥ Ability to connect the TDM channel as follows: Ñ T1 or CEPT line Ñ Pulse code modulation highway (PCM) Ñ User-deÞned interfaces ¥ Independent Tx and Rx routing paths programmed in the SI RAM ¥...
Page 596 The Time-Slot Assigner (TSA) In its simplest mode, the TSA identiÞes both Rx and Tx frames using one sync pulse and a single clock signal provided by the user externally. This mode can be enhanced to allow independent routing of Tx and Rx data on the TDM channel. The user deÞnes the length of a time slot, which need not be limited to 8 bits or even to a single contiguous position within the frame.
Page 597 The Time-Slot Assigner (TSA) Simplest TDM Example MPC857T 1 TDM Sync 1 TDM Clk SCC1 SMC1 TDM Tx Slot 3 Slot n TDM Rx Slot 3 Slot n SCC1 SMC1 More Complex TDM Example – Unique Routing MPC857T 1 TDM Sync 1 TDM Clk SCC1 SMC1...
Page 598 The Time-Slot Assigner (TSA) The TSA can support two, independent, half-duplex TDM sources, one receiving and one transmitting, using two sync inputs and two input clocks. In addition to channel programming, the TSA supports up to eight strobe outputs that may be asserted on a bit basis or a byte basis.
Page 599 The Time-Slot Assigner (TSA) 20.2.1 TSA Signals The TSA signals for TDMa are shown in Table 20-1. Table 20-1. TSA Signals Signal Description L1RSYNCa/L1TSYNCa Receive/transmit synchronization signals. Input to the MPC857T. L1RCLKa/L1TCLKa Receive/transmit clocks. Input to the MPC857T. L1RXDa Receive data. Input to the MPC857T. L1TXDa Transmit data.
Page 600 The Time-Slot Assigner (TSA) The TDM channel options with their corresponding SI RAM partitioning follow: ¥ A single TDM channel with static routingÑSI RAM is divided into Rx and Tx parts. ¥ A single TDM channel with dynamic routingÑRx and Tx RAMs are halved. Note that the SI RAM is uninitialized after power-onÑthe core should program them before enabling the TDM channel.
Page 601 The Time-Slot Assigner (TSA) When using one channel (TDMa) with dynamic changes, as in Figure 20-5, the initial current-route RAM byte addresses are as follows. ¥ 0Ð127 RXa route ¥ 256Ð383 TXa route The shadow RAMs are at addresses: ¥ 128Ð255 RXa route ¥...
Page 602 The Time-Slot Assigner (TSA) The entire SI RAM is always readable, but only the shadow RAM is safe to write. The SI status register (SISTR) can be read to determine which part of the RAM is the current-route RAM. The SI RAM pointer (SIRP) register can be used to determine which SI RAM entry is active.
Page 603 The Time-Slot Assigner (TSA) Table 20-2 describes SI RAM entry Þelds. Table 20-2. SIRAM Field Descriptions Bits Name Description LOOP Loop back on this time slot. 0 Normal mode (no loopback). 1 Loopback for this time slot. SWTR Switch transmit and receive. Valid only in Rx route RAM; ignored in the Tx route RAM. Affects operation of both L1RXDa and L1TXDa.
Page 604 The Time-Slot Assigner (TSA) L1RXD L1RXD L1TXD L1TXD Station A Station B Station A Station B Tx and Rx SI RAMn[SWTR] = 0 Tx and Rx SI RAMn[SWTR] = 1 Figure 20-8. Example Using SI RAM n [SWTR] The SWTR option allows station B to listen to transmissions from and send data to station A.
Page 605 The Time-Slot Assigner (TSA) Table 20-3. SIGMR Field Descriptions (Continued) Bits Name Description 6–7 RAM division mode. Deﬁnes the SI RAM partitioning based on whether dynamic changes are needed. 00 Static TDMa with 64 entries apiece for Rx and Tx routing. 01 Dynamic TDMa with 32 entries apiece for current-route and shadow Rx routing and 32 apiece for current-route and shadow Tx routing.
Page 606 The Time-Slot Assigner (TSA) Table 20-4. SIMODE Field Descriptions (Continued) Bits Name Description 1–3, SMCxCS SMCx clock source (NMSI mode). SMCx can take its Tx and Rx clocks from a baud rate generator 17–19 or one of four pins from the bank of clocks. However, Tx and Rx clocks must be common when connected to the NMSI.
Page 607 The Time-Slot Assigner (TSA) Table 20-4. SIMODE Field Descriptions (Continued) Bits Name Description Clock edge for TDMa. When DSCa = 0: 0 Data is sent on the rising clock edge and received on the falling edge. 1 Data is sent on the falling edge of the clock and received on the rising edge. When DSCa = 1: 0 Data is sent on the rising clock edge and received on the rising edge.
Page 608 The Time-Slot Assigner (TSA) L1CLK (CE=0) L1SYNC (FE=1) Data Bit-0 Bit-1 Bit-2 Bit-3 Bit-4 Bit-0 Bit-1 Bit-2 No Delay from Sync Latch to First Bit of Frame Figure 20-12. No Delay from Sync to Data ( x FSD = 00) Figure 20-13 and Figure 20-14 show example timings while varying SIMODE[CE] with a constant frame sync delay of one bit.
Page 609 The Time-Slot Assigner (TSA) CE=1 xFSD=00 L1CLK L1SYNC (FE=0) L1TXD (Bit-0) The L1ST is Driven from Sync. L1ST Data is Driven from Clock Low. (On Bit-0) Rx Sampled Here L1SYNC (FE=0) L1TXD (Bit-0) L1ST is Driven from Clock High. L1ST (On Bit-0) L1SYNC (FE=1)
Page 610 The Time-Slot Assigner (TSA) CE=0 xFSD=00 L1CLK L1SYNC (FE=1) L1TXD (Bit-0) The L1ST is Driven from Sync. L1ST Data is Driven From Clock High. (On Bit-0) Rx Sampled Here L1SYNC (FE=1) L1TXD (Bit-0) L1ST is Driven from Clock Low. L1ST (On Bit-0) L1SYNC (FE=0)
Page 611 The Time-Slot Assigner (TSA) Bits Field — Reset Addr 0xAEC Bits Field — GR1 SC1 R1CS T1CS Reset Addr 0xAEE Figure 20-17. SI Clock Route Register (SICR) Table 20-5 describes the SICR Þelds. Table 20-5. SICR Field Descriptions Bits Name Description 0–23 —...
Page 612 The Time-Slot Assigner (TSA) Field CSRRa CSRTa — Reset Addr 0xAE7 Figure 20-18. SI Command Register (SICMR) Table 20-6 describes the SICMR Þelds. Table 20-6. SICMR Field Descriptions Bits Name Description CSRRa Change shadow RAM for TDMa receiver/transmitter. Set by the user; cleared by the SI when the swap completes.
Page 613 The Time-Slot Assigner (TSA) 20.2.4.6 SI RAM Pointer Register (SIRP) The SI RAM pointer (SIRP) register, shown in Figure 20-20, indicates the RAM entry currently being serviced. SIRP gives the real-time status location of the SI inside a TDM frameÑuseful for debugging and synchronizing system activity with the TDMÕs activity. However, simply reading the status register SISTR is sufÞcient for most applications.
Page 614 NMSI Conﬁguration Table 20-9 describes the pointer values as affected by SIGMR[RDM]. Table 20-9. SIRP Pointer Values Conﬁguration RaPTR1/TaPTR1 point to the ﬁrst 32 entries and RaPTR2/TaPTR2 point to the second 32 entries. RaPTRn and TaPTRn point to the active Rx and Tx entries, respectively. When the SI services entries 1–32, RaPTR1/TaPTR1 is incremented and RaPTR2/TaPTR2 is continuously cleared.
Page 615 NMSI Conﬁguration RCLK1 and TCLK1 can be used as inputs to the DPLL unit, which is inside the SCC1; thus, RCLK1 and TCLK1 are not always required to reßect the actual bit rate on the line. The clock signals available to each SCC and SMC in NMSI mode are shown in Figure 20-21.
Page 616 Baud Rate Generators (BRGs) ¥ SMRXD2 ¥ SMCLK2 ¬ BRG1ÐBRG4, CLK5ÐCLK8 ¥ SMSYN2 (used only in the totally transparent protocol) Unused SCC or SMC signals can be used for other functions or conÞgured for parallel I/O. 20.4 Baud Rate Generators (BRGs) The CPM contains four independent, identical baud rate generators (BRG) that can be used with the SCC and SMCs.
Page 617 Baud Rate Generators (BRGs) the SPI, and the I C internal baud rate generator. Alternatively, the CLK2 and CLK6 pins can be conÞgured as clock sources. These external source options allow ßexible baud rate frequency generation, independent of the system frequency. Additionally, CLK2 and CLK6 allow a single external frequency to be the source for multiple BRGs.
Page 618 Baud Rate Generators (BRGs) Table 20-10 describes the BRGCn Þelds. Table 20-10. BRGC n Field Descriptions Bits Name Description 0–13 — Reserved, should be cleared. Reset BRG. Performs a software reset of the BRG identical to that of an external reset. A reset disables the BRG and drives BRGO high.
Page 619 Baud Rate Generators (BRGs) When RXD1 goes high again, the autobaud control block rewrites BRGC1[CD, DIV16] to the divide ratio found, which at high baud rates may not be exactly the Þnal rate desired (for example, 56,600 may result rather than 57,600). An interrupt can be enabled in the UART SCC event register to report that the autobaud controller rewrote BRGC1.
Page 620 Baud Rate Generators (BRGs) Table 20-11. Typical Baud Rates for Asynchronous Communication (Continued) System Frequency Baud 20 MHz 25 MHz 24.5760 MHz Rate Div16 Actual Frequency Div16 Actual Frequency Div16 Actual Frequency 149.954 300.48 300.5 2082 600.09 2603 2559 1200 1040 1200.7 1301...
Page 621 Chapter 21 Serial Communications Controller The MPC857T has one serial communications controller (SCC1), which can be conÞgured independently to implement different protocols for bridging functions, routers, and gateways, and to interface with a wide variety of standard WANs, LANs, and proprietary networks.
Page 622 Features clock recovery function is not required (that is, synchronous communication), then the DPLL can be disabled, in which case only NRZ and NRZI are supported. The SCC can be connected to its own set of pins on the MPC857T. This conÞguration is called the non-multiplexed serial interface (NMSI) and is described in Chapter 20, ÒSerial Interface.Ó...
Page 623 SCC Registers ¥ Data rate for asynchronous communication can be as high as 3.125 Mbps at 25 MHz ¥ Supports automatic control of the RTS, CTS, and CD modem signals ¥ Multi-buffer data structure for receive and send (the number of buffer descriptors (BDs) is limited only by the size of the internal dual-port RAMÑ8 bytes per BD) ¥...
Page 624 SCC Registers Table 21-1 describes GSMR_H Þelds. Table 21-1. GSMR_H Field Descriptions Name Description 0–14 — Reserved, should be cleared. Glitch detect enable. Determines whether the SCC searches for glitches on the external Rx and Tx serial clock lines. Regardless of the GDE setting, a Schmitt trigger on the input lines is used to reduce signal noise.
Page 625 SCC Registers Table 21-1. GSMR_H Field Descriptions (Continued) Name Description Rx FIFO width. 0 Receive FIFO is 32 bits wide for maximum performance; the Rx FIFO is 32 bytes for the SCC. Data is not normally written to receive buffers until at least 32 bits are received. This conﬁguration is required for HDLC-type protocols and Ethernet and is recommended for high-performance transparent protocols.
Page 626 SCC Registers Figure 21-3 shows GSMR_L. Field — EDGE TSNC RINV TINV TEND TDCR Reset Addr 0xA00 (GSMR_L1) Field RDCR RENC TENC DIAG ENR ENT MODE Reset Addr 0xA02 (GSMR_L1) Figure 21-3. GSMR_L—General SCC Mode Register (Low Order) Table 21-2 describes GSMR_L Þelds. Table 21-2.
Page 627 SCC Registers Table 21-2. GSMR_L Field Descriptions (Continued) Name Description TINV DPLL Tx input invert data. Must be zero in HDLC bus mode. 0 Do not invert. 1 Invert data before sending it to the DPLL for transmission. Used to produce FM1 from FM0 and NRZI space from NRZI mark and to invert the data stream in regular NRZ mode.
Page 628 SCC Registers Table 21-2. GSMR_L Field Descriptions (Continued) Name Description 24–25 DIAG Diagnostic mode. 00 Normal operation, CTS and CD are under automatic control. Data is received through RXD and transmitted through TXD. The SCC uses modem signals to enable or disable transmission and reception.
Page 629 SCC Registers 21.2.2 Protocol-Speciﬁc Mode Register (PSMR) The protocol implemented by the SCC is selected by its GSMR_L[MODE]. The SCC has an additional protocol-speciÞc mode register (PSMR) for conÞgurations speciÞc to the chosen protocol. The PSMR Þelds are described in the speciÞc chapters that describe each protocol.
Page 630 SCC Buffer Descriptors (BDs) The CP can be conÞgured to begin processing a new frame/buffer without waiting the normal polling time by setting TODR[TOD] after TxBD[R] is set. Because this feature favors the speciÞed TxBD, it may affect servicing of the FIFOs of other CPM controllers. Therefore, transmitting on demand should only be used when a high-priority TxBD has been prepared and enough time has passed since the last SCC transmission.
Page 631 SCC Buffer Descriptors (BDs) ¥ The word at offset + 0x4 (buffer pointer) points to the beginning of the buffer in memory (internal or external). Ñ For an RxBD, the value must be even. Ñ For a TxBD, this pointer can be even or odd. Shown in Figure 21-6, the format of Tx and Rx BDs is the same in each SCC mode.
Page 632 SCC Parameter RAM In all protocols, BDs can point to buffers in the internal dual-port RAM. However, because internal RAM is used for descriptors, buffers are usually put in external RAM, especially if they are large. Usually, the internal U bus transfers data to the buffer. The CP processes TxBDs in a straightforward manner.
Page 633 SCC Parameter RAM ¥ Rx parameter RAM can be written only when the receiver is disabled. Note the command does not stop reception, but it does allow the user to extract CLOSE RX BD data from a partially full Rx buffer. ¥...
Page 634 SCC Parameter RAM Table 21-4. SCC Parameter RAM Map for All Protocols (Continued) 0x22 TCOUNT Hword Tx internal byte count . A down-count value initialized with TxBD[Data Length] and decremented with each byte read by the supporting SDMA channel. 0x24 TTEMP Word Tx temp...
Page 635 SCC Parameter RAM To allow interrupt handling for SCC-speciÞc events, further event, mask, and status registers are provided within the SCCÕs internal memory map area; see Table 21-6. Since interrupt events are protocol-dependent, event descriptions are found in the speciÞc protocol chapters.
Page 636 SCC Parameter RAM 2. Set the SDMA conÞguration register SDCR[RAID] Þeld to 0b01 (U-bus arbitration priority level 5). 3. ConÞgure the parallel I/O registers to enable RTS, CTS, and CD if these signals are required. 4. If the time-slot assigner (TSA) is used, the serial interface (SI) must be conÞgured. If the SCC is used in NMSI mode, SICR must still be initialized.
Page 637 SCC Parameter RAM TCLK (Output) First Bit of Frame Data Last Bit of Frame Data (Output) (Input) NOTE 1. A frame includes opening and closing flags and syncs, if present in the protocol. Figure 21-9. Output Delay from RTS Asserted for Synchronous Protocols When RTS is asserted, if CTS is not already asserted, delays to the Þrst data bit depend on when CTS is asserted.
Page 638 SCC Parameter RAM TCLK Data Forced High (Output) First Bit of Frame Data RTS Forced High (Output) CTS Sampled Low Here CTS Sampled High Here (Input) CTS Lost Signaled in Frame BD NOTE 1. GSMR_H[CTSS] = 0. CTSP=0 or no CTS lost can occur. TCLK Data Forced High (Output)
Page 639 SCC Parameter RAM RCLK (Input) First Bit of Frame Data Last Bit of Frame Data (Input) CD Sampled Low Here CD Sampled High Here NOTE: 1. GSMR_H[CDS] = 0. CDP=0. 2. If CD is negated prior to the last bit of the receive frame, CD lost is signaled in the frame BD. 3.
Page 640 SCC Parameter RAM 21.4.5 Digital Phase-Locked Loop (DPLL) Operation The SCC includes a digital phase-locked loop (DPLL) for recovering clock information from a received data stream. For applications that provide a direct clock source to the SCC, the DPLL can be bypassed by selecting 1x mode for GSMR_L[RDCR, TDCR]. If the DPLL is bypassed, only NRZ or NRZI encodings are available.
Page 641 SCC Parameter RAM TENC Divided Clock TDCR HSTCLK TCLK TEND DPLL HSTCLK Transmitter 1x Mode TXEN HSTCLK Encoded Data SCCT Data TINV HSTCLK 1x Mode TENC = NRZI Figure 21-14. DPLL Transmitter Block Diagram The DPLL can be driven by one of the baud rate generator outputs or an external clock, CLKx.
Page 642 SCC Parameter RAM Table 21-7. Preamble Requirements Decoding Method Preamble Pattern Minimum Preamble Length Required NRZI Mark All zeros 8-bit NRZI Space All ones 8-bit All ones 8-bit All zeros 8-bit Manchester 101010...10 8-bit Differential Manchester All ones 8-bit The DPLL can also be used to invert the data stream of a transfer. This feature is available in all encodings, including standard NRZ format.
Page 643 SCC Parameter RAM Data NRZI Mark NRZI Space Manchester Differential Manchester Figure 21-15. DPLL Encoding Examples If the DPLL is not needed, NRZ or NRZI codings can be selected in GSMR_L[RENC, TENC]. Coding deÞnitions are shown in Table 21-8. Table 21-8. DPLL Codings Coding Description A one is represented by a high level for the duration of the bit and a zero is represented by a low level.
Page 644 SCC Parameter RAM susceptible to glitches from noise, connecting or disconnecting the physical cable from the application board, or excessive ringing on a clock line. A clock glitch occurs when more than one edge occurs in a time period that violates the minimum high or low time speciÞcation of the input clock.
Page 645 SCC Parameter RAM 21.4.7.2 Reset Sequence for the SCC Transmitter The following steps reinitialize the SCC transmit parameters to the reset state: 1. Clear GSMR_L[ENT]. 2. Make any modiÞcations then issue the command. INIT TX PARAMETERS 3. Set GSMR_L[ENT]. 21.4.7.3 General Reconﬁguration Sequence for the SCC Receiver The SCC receiver can be reconÞgured by following these steps: 1.
Page 646 SCC Parameter RAM 21-26 MPC857T PowerQUICC User’s Manual...
Page 647 Chapter 22 SCC UART Mode The universal asynchronous receiver transmitter (UART) protocol is commonly used to send low-speed data between devices. The term asynchronous is used because it is not necessary to send clocking information along with the data being sent. UART links are typically 38400 baud or less and are character-based.
Page 648 Features All standards provide handshaking signals, but some systems require only three physical linesÑTx data, Rx data, and ground. Many proprietary standards have been built around the UARTÕs asynchronous character frame, some of which implement a multidrop conÞguration where multiple stations, each with a speciÞc address, can be present on a network.
Page 649 Normal Asynchronous Mode ¥ Frame error, noise error, break, and idle detection ¥ Transmit preamble and break sequences ¥ Freeze transmission option with low-latency stop 22.2 Normal Asynchronous Mode In normal asynchronous mode, the receive shift register receives incoming data on RXD. Control bits in the UART mode register (PSMR) deÞne the length and format of the UART character.
Page 650 SCC UART Parameter RAM The synchronous UART transmit shift register sends outgoing data on TXD. Data is then clocked synchronously with the transmit clock, which can have an internal or external source. 22.4 SCC UART Parameter RAM For UART mode, the protocol-speciÞc area of the SCC parameter RAM is mapped as in Table 22-1.
Page 651 Data-Handling Methods: Character- or Message-Based Table 22-1. UART-Specific SCC Parameter RAM Memory Map (Continued) 0x50 CHARACTER1 Hword Control character 1–8. These characters deﬁne the Rx control characters on which interrupts can be generated. 0x52 CHARACTER2 Hword 0x54 CHARACTER3 Hword 0x56 CHARACTER4 Hword 0x58...
Page 652 Error and Status Reporting is useful when ßow control characters such as XON or XOFF are needed but are not part of the received message. See Section 22.9, ÒReceiving Control Characters.Ó 22.6 Error and Status Reporting Overrun, parity, noise, and framing errors are reported via the BDs and/or error counters in the UART parameter RAM.
Page 653 Multidrop Systems and Address Recognition 22.8 Multidrop Systems and Address Recognition In multidrop systems, more than two stations can be on a network, each with a speciÞc address. Figure 22-2 shows two examples of this conÞguration. Frames made up of many characters can be broadcast as long as the Þrst character is the destination address.
Page 654 Receiving Control Characters If the received control character is not rejected, it is written to the receive buffer. The receive buffer is then automatically closed to allow software to handle end-of-message characters. Control characters that are not part of the actual message, such as XOFF, can be rejected. Rejected characters bypass the receive buffer and are written directly to the received control character register (RCCR), which triggers maskable interrupt.
Page 655 Hunt Mode (Receiver) Table 22-4. Control Character Table, RCCM, and RCCR Descriptions (Continued) Offset Bits Name Description 0x62 0–7 — Reserved 8–15 RCCR Received control character register. If the newly arrived character matches and is rejected from the buffer (R = 1), the PIP controller writes the character into the RCCR and generates a maskable interrupt.
Page 656 Sending a Break (Transmitter) Table 22-5 describes TOSEQ Þelds. Table 22-5. TOSEQ Field Descriptions Name Description 0–1 — Reserved, should be cleared. Ready. Set when the character is ready for transmission. Remains 1 while the character is being sent. The CP clears this bit after transmission. Interrupt.
Page 657 Fractional Stop Bits (Transmitter) Field — — — — — — — — — — — — Reset Addr 0xA0E (DSR1) Figure 22-5. Data Synchronization Register (DSR) Table 22-6 describes DSR Þelds. Table 22-6. DSR Fields Descriptions Name Description — 1–4 Fractional stop bits.
Page 658 Handling Errors in the SCC UART Controller 22.15 Handling Errors in the SCC UART Controller The UART controller reports character reception and transmission error conditions via the BDs, the error counters, and the SCCE. Modem interface lines can be monitored by the port C pins.
Page 659 UART Mode Register (PSMR) 22.16 UART Mode Register (PSMR) For UART mode, the SCC protocol-speciÞc mode register (PSMR) is called the UART mode register. Many bits can be modiÞed while the receiver and transmitter are enabled. Figure 22-6 shows the PSMR in UART mode. Field FRZ RZS SYN DRT —...
Page 660 UART Mode Register (PSMR) Table 22-9. PSMR UART Field Descriptions (Continued) Name Description Freeze transmission. Allows the UART transmitter to pause and later continue from that point. 0 Normal operation. If the buffer was previously frozen, it resumes transmission from the next character in the same buffer that was frozen.
Page 661 SCC UART Receive Buffer Descriptor (RxBD) 22.17 SCC UART Receive Buffer Descriptor (RxBD) The CPM uses RxBDs to report on each buffer received. The CPM closes the current buffer, generates a maskable interrupt, and starts receiving data into the next buffer after one of the following occurs: ¥...
Page 662 SCC UART Receive Buffer Descriptor (RxBD) MRBLR = 8 Bytes for the SCC Rx BD 0 Buffer Status Byte 1 Length 0008 Byte 2 Buffer Full Pointer 32-Bit Buffer Pointer 8 Bytes etc. Byte 8 Rx BD 1 Buffer Status Byte 9 Length 0002...
Page 663 SCC UART Receive Buffer Descriptor (RxBD) Figure 22-8 shows the SCC UART RxBD. Offset + 0 — — — Offset + 2 Data Length Offset + 4 Rx Buffer Pointer Offset + 6 Figure 22-8. SCC UART RxBD Table 22-10 describes RxBD status and control Þelds. Table 22-10.
Page 664 SCC UART Transmit Buffer Descriptor (TxBD) Table 22-10. SCC UART RxBD Status and Control Field Descriptions (Continued) Bits Name Description Framing error. Set when a character with a framing error (a character without a stop bit) is received and located in the last byte of this buffer. A new Rx buffer is used to receive subsequent data. Parity error.
Page 665 SCC UART Event Register (SCCE) and Mask Register (SCCM) Table 22-11. SCC UART TxBD Status and Control Field Descriptions (Continued) Name Description Clear-to-send report. 0 The next buffer is sent with no delay (assuming it is ready), but if a CTS lost condition occurs, TxBD[CT] may not be set in the correct TxBD or may not be set at all.
Page 666 SCC UART Event Register (SCCE) and Mask Register (SCCM) Characters Received by UART 10 Characters Time Line Idle Line Idle Break UART SCCE IDL BRKS BRKE IDL CD Events Notes: 1. The first RX event assumes Rx buffers are 6 bytes each. 2.
Page 667 SCC UART Status Register (SCCS) Table 22-12 describes SCCE Þelds for UART mode. Table 22-12. SCCE/SCCM Field Descriptions for UART Mode Name Description 0–2 — Reserved, should be cleared. Glitch on Rx. Set when the SCC encounters an Rx clock glitch. Glitch on transmit.
Page 668 SCC UART Programming Example Table 22-13 describes UART SCCS Þelds. Table 22-13. UART SCCS Field Descriptions Bits Name Description 0–6 — Reserved, should be cleared. Idle status. Set when RXD has been a logic one for at least a full character time. 0 The line is not idle.
Page 669 S-Records Loader Application 16. Write CHARACTER1Ð8 with 0x8000. They are not used. 17. Write RCCM with 0xC0FF. It is not used. 18. Initialize the RxBD. Assume the Rx buffer is at 0x0000_1000 in main memory. Write 0xB000 to the RxBD[Status and Control], 0x0000 to RxBD[Data Length] (optional), and 0x0000_1000 to RxBD[Buffer Pointer].
Page 670 S-Records Loader Application Table 22-14. UART Control Characters for S-Records Example Character Description Line Feed Both the E and R bits should be cleared. When an end-of-line character is received, the current buffer is closed and made available to the core for processing. This buffer contains an entire S record that the processor can now check and copy to memory or disk as required.
Page 671 Chapter 23 SCC HDLC Mode HDLC (high-level data link control) is one of the most common protocols in the data link layer, layer 2 of the OSI model. Many other common layer 2 protocols, such as SDLC, SS#7, AppleTalk, LAPB, and LAPD, are based on HDLC and its framing structure in particular.
Page 672 SCC HDLC Features 23.1 SCC HDLC Features The main features of the SCC in HDLC mode are follows: ¥ Flexible buffers with multiple buffers per frame ¥ Separate interrupts for frames and buffers (Rx and Tx) ¥ Received-frames threshold to reduce interrupt overhead ¥...
Page 673 SCC HDLC Channel Frame Reception command can be used to expedite critical data ahead of previously STOP TRANSMIT linked buffers or to support efÞcient error handling. When the SCC receives a STOP command, it sends idles or ßags instead of the current frame until it receives a TRANSMIT command.
Page 674 SCC HDLC Parameter RAM Table 23-1. HDLC-Specific SCC Parameter RAM Memory Map Offset Name Width Description 0x30 — Word Reserved 0x34 C_MASK Word CRC mask. For the 16-bit CRC-CCITT, initialize with 0x0000_F0B8. For 32-bit CRC-CCITT, initialize with 0xDEBB_20E3. 0x38 C_PRES Word CRC preset.
Page 675 Programming the SCC HDLC Controller Figure 23-2 shows 16- and 8-bit address recognition. 16-Bit Address Recognition 8-Bit Address Recognition Flag Address Address Control Flag Address Control etc. etc. 0x7E 0x68 0xAA 0x44 0x7E 0x55 0x44 HMASK 0xFFFF HMASK 0x00FF HADDR1 0xAA68 HADDR1 0xXX55...
Page 676 Handling Errors in the SCC HDLC Controller Receive commands are described in Table 23-3. Table 23-3. Receive Commands Command Description After a hardware or software reset, once the SCC is enabled in the GSMR, the receiver is ENTER HUNT automatically enabled and uses the ﬁrst BD in the RxBD table. While the SCC is looking for the MODE beginning of a frame, that SCC is in hunt mode.
Page 677 HDLC Mode Register (PSMR) Table 23-5. Receive Errors (Continued) Error Description Abort Occurs when seven or more consecutive ones are received. When this occurs while receiving a Sequence frame, the channel closes the buffer, sets RxBD[AB] and generates a maskable RXF interrupt. The channel also increments the abort sequence counter ABTSC.
Page 678 SCC HDLC Receive Buffer Descriptor (RxBD) Table 23-6. PSMR HDLC Field Descriptions (Continued) Bits Name Description Retransmit enable. 0 No retransmission. 1 Automatic frame retransmission is enabled. Particularly useful in the HDLC bus protocol and ISDN applications where multiple HDLC controllers can collide. Note that retransmission occurs only if a lost CTS occurs on the ﬁrst or second buffer of the frame.
Page 679 SCC HDLC Receive Buffer Descriptor (RxBD) Table 23-7 describes HDLC RxBD status and control Þelds. Table 23-7. SCC HDLC RxBD Status and Control Field Descriptions Bits Name Description Empty. 0 The buffer is full or reception stopped because of an error. The core can read or write to any ﬁelds of this RxBD.
Page 680 SCC HDLC Receive Buffer Descriptor (RxBD) MRBLR = 8 Bytes for the SCC Receive BD 0 Buffer Status Address 1 Length 0x0008 Address 2 Buffer Full Pointer 32-Bit Buffer Pointer 8 Bytes Control Byte Information (I-Field) Bytes Receive BD 1 Buffer Status Last I-Field Byte...
Page 681 SCC HDLC Transmit Buffer Descriptor (TxBD) 23.10 SCC HDLC Transmit Buffer Descriptor (TxBD) The CPM uses the TxBD, shown in Figure 23-6, to conÞrm transmissions and indicate error conditions. Offset + 0 — — Offset + 2 Data Length Offset + 4 Tx Buffer Pointer Offset + 6 Figure 23-6.
Page 682 HDLC Event Register (SCCE)/HDLC Mask Register (SCCM) 23.11 HDLC Event Register (SCCE)/HDLC Mask Register (SCCM) The SCC event register (SCCE) is used as the HDLC event register to report events recognized by the HDLC channel and to generate interrupts. When an event is recognized, the SCC sets the corresponding SCCE bit.
Page 683 HDLC Event Register (SCCE)/HDLC Mask Register (SCCM) Table 23-9. SCCE/SCCM Field Descriptions (Continued) Bits Name Description Transmit buffer. Enabled by setting TxBD[I]. TXB is set when a buffer is sent on the HDLC channel. For the last buffer in the frame, TXB is not set before the last bit of the closing ﬂag begins its transmission; otherwise, it is set after the last byte of the buffer is written to the Tx FIFO.
Page 684 SCC HDLC Status Register (SCCS) 23.12 SCC HDLC Status Register (SCCS) The SCC status register (SCCS), shown in Figure 23-9, permits monitoring of real-time status conditions on RXD. The real-time status of CTS and CD are part of the port C parallel I/O.
Page 685 SCC HDLC Programming Examples 23.13.1 SCC HDLC Programming Example #1 The following initialization sequence is for the SCC HDLC channel with an external clock. RTS1, CTS1, and CD1 are active; CLK3 is used for both the HDLC receiver and transmitter. 1.
Page 686 HDLC Bus Mode with Collision Detection 22. Write 0x4000_0000 to the CPM interrupt mask register (CIMR) to allow SCC1 to generate a system interrupt. The CICR should also be initialized. 23. Write 0x0000_0000 to GSMR_H1 to enable normal CTS and CD behavior with idles (not ßags) between frames.
Page 687 HDLC Bus Mode with Collision Detection or T1.605 and cannot replace devices that implement these protocols. Instead, it is more suited to non-ISDN LAN and point-to-multipoint conÞgurations. Review the basic features of the I.430 and T1.605 before learning about the HDLC bus. The I.430 and T1.605 deÞne a way to connect eight terminals over the D-channel of the S/T ISDN bus.
Page 688 HDLC Bus Mode with Collision Detection + 3.3 V HDLC Bus LAN HDLC Bus HDLC Bus HDLC Bus Controller Controller Controller RCLK/TCLK RCLK/TCLK RCLK/TCLK Clock Master Master Master NOTES 1. Transceivers may be used to extend the LAN size. 2. The TXD pins of slave devices should be configured to open-drain in the port C parallel I/O port. 3.
Page 689 HDLC Bus Mode with Collision Detection 23.14.1 HDLC Bus Features The main features of the HDLC bus are as follows: ¥ Superset of the HDLC controller features ¥ Automatic HDLC bus access ¥ Automatic retransmission in case of collision ¥ May be used with the NMSI or a TDM bus ¥...
Page 690 HDLC Bus Mode with Collision Detection If both the destination address and source address are included in the HDLC frame, then a predeÞned priority of stations results; if two stations begin to transmit simultaneously, they necessarily detect a collision no later than the end of the source address. The HDLC bus priority mechanism ensures that stations share the bus equally.
Page 691 HDLC Bus Mode with Collision Detection + 3.3V Local HDLC Bus Line Driver (1-Bit Delay) HDLC Bus HDLC Bus Controller Controller NOTES: 1. The TXD pins of slave devices should be configured to open-drain in the port C parallel I/O port. 2.
Page 692 HDLC Bus Mode with Collision Detection the TDM transmission line; stations that share a time slot use the HDLC bus protocol to control access to the local bus. + 3.3V Local HDLC Bus Line Driver L1RXD L1TXD L1RXD L1TXD L1RXD L1TXD L1RXD L1TXD...
Page 693 HDLC Bus Mode with Collision Detection 23.14.6.1 Programming GSMR and PSMR for the HDLC Bus Protocol To program the protocol-speciÞc mode register (PSMR), set the bits as described below: ¥ ConÞgure NOF as preferred ¥ Set RTE and BUS to 1 ¥...
Page 694 HDLC Bus Mode with Collision Detection 23-24 MPC857T PowerQUICC User’s Manual...
Page 695 Chapter 24 SCC AppleTalk Mode AppleTalk is a set of protocols developed by Apple Computer, Inc. to provide a LAN service between Macintosh computers and printers. Although AppleTalk can be implemented over a variety of physical and link layers, including Ethernet, AppleTalk protocols have been most closely associated with the LocalTalk physical and link-layer protocol, an HDLC-based protocol that runs at 230.4 kbps.
Page 696 Features The control byte within the LocalTalk frame indicates the type of frame. Control byte values from 0x01Ð0x7F are data frames; control byte values from 0x80Ð0xFF are control frames. Four control frames are deÞned: ¥ ENQÑEnquiry ¥ ACKÑEnquiry acknowledgment ¥ RTSÑRequest to send a data frame ¥...
Page 697 Connecting to AppleTalk 24.3 Connecting to AppleTalk As shown in Figure 24-2, the MPC857T connects to LocalTalk, and, using TXD, RTS, and RXD, is an interface for the RS-422 transceiver. The RS-422, in turn, is an interface for the LocalTalk connector. Although it is not shown, a passive RC circuit is recommended between the transceiver and connector.
Page 698 Programming the SCC in AppleTalk Mode 4. Set the TENC and RENC bits to 0b010 (FM0). 5. Clear TEND for default operation. 6. Set TPP to 0b11 for a preamble pattern of all ones. 7. Set TPL to 0b000 to transmit the next frame with no synchronization sequence and to 001 to transmit the next frame with the LocalTalk synchronization sequence.
Page 699 Chapter 25 SCC Asynchronous HDLC Mode and IrDA Asynchronous HDLC and IrDA uses HDLC framing techniques with UART-type characters. This document refers to both protocols collectively as asynchronous HDLC. The asynchronous HDLC protocol is typically used as the physical layer for point-to-point protocol (PPP) and the infrared link access protocol (IrLAP).
Page 700 Asynchronous HDLC Frame Transmission Processing 25.2 Asynchronous HDLC Frame Transmission Processing The SCC in asynchronous HDLC mode (asynchronous HDLC controller) works with minimal core intervention. When the core enables the transmitter and sets TxBD[R] in the Þrst BD of the table, the asynchronous HDLC controller fetches data from memory and starts sending the frame.
Page 701 Transmitter Transparency Encoding updates RxBD[Data Length] with the total frame length, including the CRC bytes. The controller sets RxBD[L], writes the frame status bits, and clears RxBD[E] (if RxBD[CM] is zero). It then sets SCCE[RXF], which indicates that a frame was received and is in memory.
Page 702 Exceptions to RFC 1549 Rx CHAR True CHAR < 0x20 False True True Mapped XOR_NEXT False False True True CHAR=CTRL ESC CHAR=Closing Flag False False XOR_NEXT=1 CHAR Å 0x20 True CHAR=Closing Flag Exit XOR_NEXT=0 False Write CHAR to Buffer End of Frame Exit Abort Figure 25-2.
Page 703 Asynchronous HDLC Channel Implementation 25.7 Asynchronous HDLC Channel Implementation The following points are speciÞc to asynchronous HDLC channel implementation: ¥ Flag sequenceÑThe transmitter automatically generates the opening and closing ßags. The receiver removes opening and closing ßags before writing a frame to memory and receives frames with only one shared ßag between frames, ignoring multiple ßags.
Page 704 Conﬁguring GSMR and DSR for Asynchronous HDLC Table 25-1. Asynchronous HDLC-Specific SCC Parameter RAM Memory Map (Continued) Offset Name Width Description 0x48 — Hword Reserved 0x4A RFTHR Hword Received frames threshold. Number of Rx frames needed to trigger SCCE[RXF] 0x4C —...
Page 705 Programming the Asynchronous HDLC Controller 25.9.1 General SCC Mode Register (GSMR) Table 25-2 shows asynchronous HDLC-speciÞc information for the GSMR. Table 25-2. Asynchronous HDLC-Specific GSMR Field Descriptions Name Description Rx FIFO width (GSMR_H[26]) 0 Do not use. 1 Low-latency operation—for character-oriented protocols like UART, BISYNC, and asynchronous HDLC. The Rx FIFO is 8 bits wide and the Rx FIFO is one-fourth its normal size (8 bytes for SCC1).
Page 706 Handling Errors in the Asynchronous HDLC Controller Table 25-3. Transmit Commands Command Description Sends the asynchronous HDLC abort sequence (0x7D;0x7E for PPP, 0x7D; 0xC1 for IrLAP) and STOP disables data transmission. If the asynchronous HDLC controller receives this command during TRANSMIT frame transmission, the abort sequence is put in the FIFO and the transmitter does not try to send more data from the current BD or advance to the next TxBD.
Page 707 SCC Asynchronous HDLC Registers Table 25-6 describes reception errors. Table 25-6. Receive Errors Error Description Overrun SCC1 has 32-byte Rx FIFOs. Overrun occurs when the CP cannot keep up with the data rate or the SDMA channel cannot write the received data to memory. The previous data byte and frame status are lost.
Page 708 SCC Asynchronous HDLC Registers Table 25-7 describes SCCE/SCCM Þelds. Table 25-7. SCCE/SCCM Field Descriptions Bits Name Description 0–2 — Reserved, should be cleared. Glitch on Rx. Set when the SCC ﬁnds a Rx clock glitch. Glitch on Tx. Set when the SCC ﬁnds a Tx clock glitch. 5–6 —...
Page 709 SCC Asynchronous HDLC RxBDs Table 25-8 describes asynchronous HDLC SCCS Þelds. Table 25-8. Asynchronous HDLC SCCS Field Descriptions Bits Name Description 0–6 — Reserved, should be cleared. Idle status. Set when RXD has been a logic one for at least a full character time. 0 The line is not idle.
Page 710 SCC Asynchronous HDLC RxBDs Offset + 0 — — BRK BOF — Offset + 2 Data Length Offset + 4 Rx Buffer Pointer Offset + 6 Figure 25-7. SCC Asynchronous HDLC RxBDs Table 25-10 describes the SCC asynchronous HDLC RxBD status and control Þelds. Table 25-10.
Page 711 SCC Asynchronous HDLC TxBDs Table 25-10. Asynchronous HDLC RxBD Status and Control Field Descriptions (Continued) Bits Name Description Overrun. Set when a receiver overrun occurs during frame reception. Carrier detect lost. Set when CD is negated during frame reception. The data length and buffer pointer Þelds are described in Section 21.3, ÒSCC Buffer Descriptors (BDs).Ó...
Page 712 Differences between HDLC and Asynchronous HDLC Table 25-11. Asynchronous HDLC TxBD Status and Control Field Descriptions (Continued) Bits Name Description Continuous mode. 0 Normal operation. 1 The CP does not clear R after this BD is closed, allowing its buffer to be resent when the CP next accesses this BD.
Page 713 SCC Asynchronous HDLC Programming Example 25.17 SCC Asynchronous HDLC Programming Example The following example shows initialization for an SCC in asynchronous HDLC mode. 1. Initialize SDCR. 2. In NMSI mode, conÞgure ports A and C to enable RXD, TXD, CTS, CD, and RTS. In other modes, conÞgure the TSA and its pins.
Page 714 SCC Asynchronous HDLC Programming Example 25-16 MPC857T PowerQUICC User’s Manual...
Page 715 Chapter 26 SCC BISYNC Mode The byte-oriented BISYNC protocol was developed by IBM for use in networking products. There are three classes of BISYNC framesÑtransparent, nontransparent with header, and nontransparent without header, shown in Figure 26-1. The transparent frame type in BISYNC is not related to transparent mode, discussed in Chapter 28, ÒSCC Transparent Mode.Ó...
Page 716 Features transmission, an underrun must not occur between the DLE and its following character. This failure mode cannot occur with the MPC857T. The SCC can be conÞgured as a BISYNC controller to handle basic BISYNC protocol in normal and transparent modes. The controller can work with the time-slot assigner (TSA) or nonmultiplexed serial interface (NMSI).
Page 717 SCC BISYNC Channel Frame Reception interrupt is issued according to TxBD[I]. TxBD[I] controls whether interrupts are generated after transmission of each buffer, a speciÞc buffer, or each block. The controller then proceeds to the next BD. If no additional buffers have been sent to the controller for transmission, an in-frame underrun is detected and the controller starts sending syncs or idles.
Page 718 SCC BISYNC Parameter RAM 26.4 SCC BISYNC Parameter RAM When BISYNC mode is selected in GSMR_L[MODE], the protocol-speciÞc area of the SCC parameter RAM is mapped as in Table 26-1. Table 26-1. SCC BISYNC Parameter RAM Memory Map Offset Name Width Description 0x30...
Page 719 SCC BISYNC Commands 26.5 SCC BISYNC Commands Transmit and receive commands are issued to the CP command register (CPCR). Transmit commands are described in Table 26-2. Table 26-2. Transmit Commands Command Description After hardware or software is reset and the channel is enabled in the GSMR, the channel is in transmit STOP enable mode and starts polling the ﬁrst BD every 64 transmit clocks.
Page 720 SCC BISYNC Control Character Recognition 26.6 SCC BISYNC Control Character Recognition The BISYNC controller recognizes special control characters that customize the protocol implemented by the BISYNC controller and aid its operation in a DMA-oriented environment. They are used for receive buffers longer than one byte. In single-byte buffers, each byte can easily be inspected so control character recognition should be disabled.
Page 721 BISYNC SYNC Register (BSYNC) Table 26-4 describes control character table and RCCM Þelds. Table 26-4. Control Character Table and RCCM Field Descriptions Offset Name Description 0x42–0x50 0 End of table. 0 This entry is valid. The lower eight bits are checked against the incoming character.
Page 722 SCC BISYNC DLE Register (BDLE) Table 26-5 describes BSYNC Þelds. Table 26-5. BSYNC Field Descriptions Bits Name Description Valid. If V = 1 and the receiver is not in hunt mode when a SYNC character is received, this character is discarded. 1–7 —...
Page 723 Sending and Receiving the Synchronization Sequence 26.9 Sending and Receiving the Synchronization Sequence The BISYNC channel can be programmed to send and receive a synchronization pattern deÞned in the DSR. GSMR_H[SYNL] deÞnes pattern length, as shown in Table 26-7. The receiver synchronizes on this pattern.
Page 724 BISYNC Mode Register (PSMR) Table 26-9 describes receive errors. Receive Errors Table 26-9. Error Description Overrun The controller maintains a receiver FIFO for receiving data. The CP begins programming the SDMA channel (if the buffer is in external memory) and updating the CRC when the ﬁrst byte is received in the Rx FIFO.
Page 725 BISYNC Mode Register (PSMR) Table 26-10 describes PSMR Þelds. Table 26-10. PSMR Field Descriptions Bits Name Description 0–3 Minimum number of SYN1–SYN2 pairs (deﬁned in DSR) sent between or before messages.If NOS = 0000, one pair is sent. If NOS = 1111, 16 pairs are sent. The entire pair is always sent, regardless of how GSMR[SYNL) is set.
Page 726 SCC BISYNC Receive BD (RxBD) 26.12 SCC BISYNC Receive BD (RxBD) The CP uses BDs to report on each buffer received. It closes the buffer, generates a maskable interrupt, and starts receiving data into the next buffer after any of the following: ¥...
Page 727 SCC BISYNC Transmit BD (TxBD) Table 26-11. SCC BISYNC RxBD Status and Control Field Descriptions (Continued) Bits Name Description Continuous mode. 0 Normal operation. 1 The CP does not clear E after this BD is closed; the buffer is overwritten when the CP accesses this BD next.
Page 728 SCC BISYNC Transmit BD (TxBD) Table 26-12 describes SCC BISYNC TxBD status and control Þelds. Table 26-12. SCC BISYNC TxBD Status and Control Field Descriptions Bits Name Description Ready. 0 The buffer is not ready for transmission. The current BD and buffer can be updated. The CP clears R after the buffer is sent or after an error condition.
Page 729 BISYNC Event Register (SCCE)/BISYNC Mask Register (SCCM) Table 26-12. SCC BISYNC TxBD Status and Control Field Descriptions Bits Name Description Underrun. Set when the BISYNC controller encounters a transmitter underrun error while sending the associated data buffer. The CPM writes UN after it sends the associated buffer. CTS lost.
Page 730 SCC Status Registers (SCCS) Table 26-13. SCCE/SCCM Field Descriptions Bits Name Description Receive character. Set when a character is received and written to the buffer. Busy. Set when a character is received and discarded due to a lack of buffers. The receiver resumes reception after an command.
Page 731 SCC BISYNC Programming Example To accomplish this, set SCCM[RCH] to enable an interrupt on every received byte so software can analyze each byte. After analyzing the initial characters of a block, either set PSMR[RTR] or issue a command. For example, if a DLE-STX is RESET BCS CALCULATION received, enter transparent mode.
Page 732 SCC BISYNC Programming Example 5. Connect the SCC1 to the NMSI and clear SICR[SC1]. 6. Initialize the SDMA conÞguration register (SDCR). 7. Assuming one RxBD at the beginning of dual-port RAM followed by one TxBD, write RBASE with 0x0000 and TBASE with 0x0008. 8.
Page 733 SCC BISYNC Programming Example Note that after 5 bytes are sent, the TxBD is closed. The buffer is closed after 16 bytes are received. Any received data beyond 16 bytes causes a busy (out-of-buffers) condition since only one RxBD is prepared. Chapter 26.
Page 734 SCC BISYNC Programming Example 26-20 MPC857T PowerQUICC User’s Manual...
Page 735 Chapter 27 SCC Ethernet Mode The Ethernet IEEE 802.3 protocol is a widely used LAN protocol based on the carrier sense multiple access/collision detect (CSMA/CD) approach. Because Ethernet and IEEE 802.3 protocols are similar and can coexist on the same LAN, both are referred to as Ethernet in this manual, unless otherwise noted.
Page 736 Ethernet on the MPC857T a random period of time, called a backoff, before trying to retransmit. Once the backoff time expires, the station waits for silence on the LAN before retransmitting, which is called a retry. If the frame cannot be sent within 15 retries, an error occurs 10-Mbps Ethernet transmits at 0.8 µs per byte.
Page 737 Features controller bypasses the on-chip DPLLs and uses the external system interface adaptor on the EEST instead. The on-chip DPLL cannot be used for low-speed (1-Mbps) Ethernet either because it cannot properly detect start-of-frame or end-of-frame. Note that the CPM of the MPC857T requires a minimum system clock frequency of 24 MHz to support Ethernet.
Page 738 Learning Ethernet on the MPC857T Ñ Lost carrier sense Ñ Underrun Ñ Number of collisions exceeded the maximum allowed Ñ Number of retries per frame Ñ Deferred frame indication Ñ Late collision ¥ Receiver network management and diagnostics Ñ CRC error indication Ñ...
Page 739 Connecting the MPC857T to Ethernet 27.4 Connecting the MPC857T to Ethernet The basic interface to the external EEST chip consists of the following Ethernet signals: ¥ Receive clock (RCLK)Ña CLKx signal routed through the bank of clocks on the MPC857T. ¥...
Page 740 SCC Ethernet Channel Frame Transmission The EEST has similar names for its connection to the above seven MPC857T signals. The EEST also provides a loopback input so the MPC857T can perform external loopback testing, which can be controlled by any available MPC857T parallel I/O signal. There are additional pins for interfacing with an optional external content-addressable memory (CAM) described in Section 27.7, ÒThe Content-Addressable Memory (CAM) Interface.Ó...
Page 741 SCC Ethernet Channel Frame Reception To send expedited data before previously linked buffers or for error situations, the command can be used to rearrange transmit queue before the GRACEFUL STOP TRANSMIT CPM sends all the frames; the Ethernet controller stops immediately if no transmission is in progress or it will keep sending until the current frame either Þnishes or terminates with a collision.
Page 742 The Content-Addressable Memory (CAM) Interface data length written to the last BD in the Ethernet frame is the length of the entire frame and it enables the software to correctly recognize the frame-too-long condition. When the receive frame is complete, the Ethernet controller can sample one byte from the port B parallel I/O and append this byte to the end of the last RxBD in the frame.
Page 743 The Content-Addressable Memory (CAM) Interface is set. The Ethernet controller samples this information tag as the last FCS byte is read from the receive FIFO. The CAM control logic must provide the information tag no later than when RENA is negated at the end of a noncollision frame and should be held stable on PB(16Ð23) until SDACK(1Ð2) indicate that the tag byte is being written to memory.
Page 744 The Content-Addressable Memory (CAM) Interface written to memory and are not used for other protocols. The CAM control logic uses these signals simultaneously to enable the CAM writes with system memory writes. The advantage of the CAM capturing frame data as it is written to system memory is that the data is already in parallel form when it leaves the MPC857T.
Page 745 SCC Ethernet Parameter RAM The SDACK1 and SDACK2 signals are asserted during all bus cycle writes of the frame data. One SDACK1/SDACK2 combination identiÞes the Þrst 32 bits of the frame, another identiÞes all mid-frame data, and a third identiÞes the last 32-bit bus write of the frame only if the tag byte is appended.
Page 746 SCC Ethernet Parameter RAM Table 27-1. SCC Ethernet Parameter RAM Memory Map (Continued) Offset Name Width Description 0x4A MFLR Hword Maximum frame length register (typically 1518 decimal). The Ethernet controller checks the length of an incoming Ethernet frame against this limit. If it is exceeded, the rest of the frame is discarded and LG is set in the last BD of that frame.
Page 747 Programming the Ethernet Controller Table 27-1. SCC Ethernet Parameter RAM Memory Map (Continued) Offset Name Width Description 0x78 P_PER Hword Persistence. Lets the Ethernet controller be less aggressive after a collision. Normally, 0x0000. It can be a value between 1 and 9 (1 is most aggressive). The value is added to the retry count in the backoff algorithm to reduce the chance of transmission on the next time slot.
Page 748 SCC Ethernet Commands 27.10 SCC Ethernet Commands Transmit and receive commands are issued to the CP command register (CPCR). Table 27-2 describes transmit commands. Table 27-2. Transmit Commands Command Description When used with the Ethernet controller, this command violates a speciﬁc behavior of an Ethernet/IEEE STOP 802.3 station.
Page 749 SCC Ethernet Address Recognition 27.11 SCC Ethernet Address Recognition The Ethernet controller can Þlter received frames based on different addressing typesÑphysical (individual), group (multicast), broadcast (all-ones group address), and promiscuous. The difference between an individual address and a group address is determined by the I/G bit in the destination address Þeld.
Page 750 Hash Table Algorithm In group address recognition, the controller determines whether the group address is a broadcast address. If broadcast addresses are enabled, the frame is accepted, but if the group address is not a broadcast address, address recognition can be performed on multiple group addresses using the GADDRn hash table.
Page 751 Interpacket Gap Time 27.13 Interpacket Gap Time The receiver receives back-to-back frames with a minimum interpacket spacing of 9.6 µs. In addition, after the backoff algorithm, the transmitter waits for carrier sense to be negated before resending the frame. Retransmission begins 9.6 µs after carrier sense is negated if it stays negated for at least 6.4 µs.
Page 752 Handling Errors in the Ethernet Controller 27.17 Handling Errors in the Ethernet Controller The Ethernet controller reports frame reception and transmission error conditions using channel BDs, error counters, and SCCE. Table 27-4 describes transmission errors. Table 27-4. Transmission Errors Error Description Transmitter underrun If this error occurs, the channel sends 32 bits that ensures a CRC error, stops sending the...
Page 753 Ethernet Mode Register (PSMR) Field RSH IAM PRO BRO SBT Reset 0000_0000_0000_0000 Addr 0xA08 (PSMR1) Figure 27-7. Ethernet Mode Register (PSMR) Table 27-6 describes PSMR Þelds. Table 27-6. PSMR Field Descriptions Bits Name Description Heartbeat checking. 0 No heartbeat checking is performed. Do not wait for a collision after transmission. 1 Wait 20 transmit clocks or 2 µs for a collision asserted by the transceiver after transmission.
Page 754 SCC Ethernet Receive Buffer Descriptor Table 27-6. PSMR Field Descriptions Bits Name Description 12–14 NIB Number of ignored bits. Determines how soon after RENA assertion the Ethernet controller should begin looking for the start frame delimiter. Typically NIB = 101 (22 bits). 000 Begin searching 13 bits after the assertion of RENA.
Page 755 SCC Ethernet Receive Buffer Descriptor Table 27-7. SCC Ethernet RxBD Status and Control Field Descriptions (Continued) Bits Name Description First in frame. The Ethernet controller sets this bit when this buffer is the ﬁrst one in a frame. 0 The buffer is not the ﬁrst one in a frame. 1 The buffer is the ﬁrst one in a frame.
Page 756 SCC Ethernet Transmit Buffer Descriptor MRBLR = 64 Bytes for the SCC Receive BD 0 Buffer Status Destination Address (6) Length 0x0040 Source Address (6) Buffer Full Pointer 32-Bit Buffer Pointer 64 Bytes Type/Length (2) Data Bytes (50) Receive BD 1 Buffer Status CRC Bytes (4)
Page 757 SCC Ethernet Transmit Buffer Descriptor Offset + 0 Offset + 2 Data Length Offset + 4 Tx Data Buffer Pointer Offset + 6 Figure 27-10. SCC Ethernet TxBD Table 27-8 describes TxBD status and control Þelds. Table 27-8. SCC Ethernet TxBD Status and Control Field Descriptions Bits Name Description...
Page 758 SCC Ethernet Event Register (SCCE)/Mask Register (SCCM) Table 27-8. SCC Ethernet TxBD Status and Control Field Descriptions (Continued) Bits Name Description Underrun. Set when the Ethernet controller encounters a transmitter underrun while sending the buffer. The Ethernet controller writes UN after it ﬁnishes sending the buffer. Carrier sense lost.
Page 759 SCC Ethernet Programming Example Frame Received in Ethernet Stored in Rx Buffer Time P SFD DA SA Line Idle Line Idle RENA Ethernet SCCE Events NOTES 1. RXB event assumes receive buffers are 64 bytes each. 2. The RENA events, if required, must be programmed in the port C parallel I/O, not in the SCC itself. 3.
Page 760 SCC Ethernet Programming Example 3. Do not enable the RTS1 (TENA) pin yet because it is still functioning as RTS and transmission on the LAN could begin accidentally. 4. ConÞgure port A to enable the CLK1 and CLK2 pins. Set PAPAR[6, 7] and clear PADIR[6, 7].
Page 761 SCC Ethernet Programming Example 26. Initialize the TxBD and assume the Tx data frame is at 0x0000_2000 in main memory and contains fourteen 8-bit characters (destination and source addresses plus the type Þeld). Write 0xFC00 to TxBD[Status and Control], add PAD to the frame and generate a CRC.
Page 762 SCC Ethernet Programming Example 27-28 MPC857T PowerQUICC User’s Manual...
Page 763 Chapter 28 SCC Transparent Mode Transparent mode (also called totally transparent or promiscuous mode) provides a clear channel on which the SCC can send or receive serial data without bit-level manipulation. Software implements protocols run over transparent mode. The SCC in transparent mode functions as a high-speed serial-to-parallel and parallel-to-serial converter.
Page 764 SCC Transparent Channel Frame Transmission Process 28.2 SCC Transparent Channel Frame Transmission Process The transparent transmitter is designed to work almost no intervention from the core. When the core enables the SCC transmitter in transparent mode, it starts sending idles, which are logic high or encoded ones, as programmed in GSMR_L[TEND].
Page 765 Achieving Synchronization in Transparent Mode maskable interrupt. The receiver reverts to hunt mode when an ENTER HUNT MODE command or an error is received. If GSMR_H[REVD] is set, the bit order of each byte is reversed before it is written to memory. Setting GSMR_H[RFW] reduces receiver latency by making the receive FIFO smaller, which may cause receiver overruns at higher transmission speeds.
Page 766 Achieving Synchronization in Transparent Mode 28.4.1.2 External Synchronization Signals If GSMR_H[SYNL] is 0b00, the transmitter uses CTS and the receiver uses CD to begin the sequence. These signals share two optionsÑpulsing and sampling. GSMR_H[CDP] and GSMR_H[CTSP] determine whether CD or CTS need to be asserted only once to begin reception/transmission or whether they must remain asserted for the duration of the transparent frame.
Page 767 Achieving Synchronization in Transparent Mode MPC857T (A) MPC857T (B) BRGOx CLKx CLKx BRGOx BRGOx (Output is CLKx Input) (Output is RXD Input) Last Bit of Frame Data First Bit of Frame Data or CRC (Output is CD Input) TxBD[L] = 1 Causes Negation of RTS CD Lost Condition Terminates Reception of Frame Notes: •...
Page 768 CRC Calculation in Transparent Mode 28.4.2 Synchronization and the TSA A transparent-mode SCC using the time-slot assigner can synchronize either on a user-deÞned in-line pattern or by inherent synchronization. Note that when using the TSA, a newly-enabled transmitter sends from 10 to 15 frames of idles before sending the actual transparent data due to start-up requirements of the TDM.
Page 769 SCC Transparent Commands Table 28-2. SCC Transparent Parameter RAM Memory Map Offset Name Width Description 0x 30 CRC_ Long CRC preset for totally transparent. For the 16-bit CRC-CCITT, initialize with 0x0000_FFFF. For the 32-bit CRC-CCITT, initialize with 0xFFFF_FFFF and for the CRC-16, initialize with ones (0x0000_FFFF) or zeros (0x0000_0000).
Page 770 Handling Errors in the Transparent Controller Table 28-4 describes receive commands. Table 28-4. Receive Commands Command Description After hardware or software is reset and the channel is enabled, the channel is in receive enable mode ENTER HUNT and uses the ﬁrst BD in the table. forces the transparent receiver to the current MODE ENTER HUNT MODE...
Page 771 SCC Transparent Receive Buffer Descriptor (RxBD) (transmitter or receiver) is running the transparent protocol, the other half (receiver or transmitter) can support another protocol. In such a case, use the PSMR for the non-transparent protocol. 28.10 SCC Transparent Receive Buffer Descriptor (RxBD) The CPM reports information about the received data for each buffer using an RxBD, closes the current buffer, generates a maskable interrupt, and starts receiving data into the...
Page 772 SCC Transparent Transmit Buffer Descriptor (TxBD) Table 28-7. SCC Transparent RxBD Status and Control Field Descriptions (Contin- Bits Name Description Last in frame. Set by the transparent controller when this buffer is the last in a frame, which occurs when CD is negated (if GSMR_H[CDP] = 0) or an error is received. If an error is received, one or more of RxBD[OV, CD, DE] are set.
Page 773 SCC Transparent Transmit Buffer Descriptor (TxBD) Offset + 0 — — Offset + 2 Data Length Offset + 4 Tx Buffer Pointer Offset + 6 Figure 28-3. SCC Transparent Transmit Buffer Descriptor (TxBD) Table 28-8 describes SCC Transparent TxBD status and control Þelds. Table 28-8.
Page 774 SCC Transparent Event Register (SCCE)/Mask Register (SCCM) 28.12 SCC Transparent Event Register (SCCE)/Mask Register (SCCM) When the SCC is in transparent mode, the SCC event register (SCCE) functions as the transparent event register to report events recognized by the transparent channel and to generate interrupts.
Page 775 SCC Status Register in Transparent Mode (SCCS) 28.13 SCC Status Register in Transparent Mode (SCCS) The SCC status register (SCCS) allows monitoring of real-time status conditions on the RXD line. The real-time status of CTS and CD are part of the port C parallel I/O. Field —...
Page 776 SCC1 Transparent Programming Example 7. Write RBASE with 0x0000 and TBASE with 0x0008 in the SCC1 parameter RAM to point to one RxBD at the beginning of dual-port RAM followed by one TxBD. 8. Write 0x0001 to CPCR to execute the command for SCC1.
Page 777 Chapter 29 Serial Management Controllers (SMCs) The two serial management controllers (SMCs) are full-duplex ports that can be conÞgured independently to support one of three protocolsÑUART, transparent, or general-circuit interface (GCI). Simple UART operation is used to provide a debug/monitor port in an application, which allows the SCC to be free for other purposes.
Page 778 SMC Features SYNC Control Control Registers Logic Peripheral Bus Data Data Register Register Shifter Shifter Figure 29-1. SMC Block Diagram The receive data source can be L1RXDa if the SMC is connected to TDM channel of the SI or SMRXD if it is connected to the NMSI. Likewise, the transmit data source can be L1TXD if using TDM or SMTXD if using the NMSI.
Page 779 Common SMC Settings and Conﬁgurations 29.2 Common SMC Settings and Conﬁgurations The following sections describe settings and conÞgurations that are common to the serial management controllers. 29.2.1 SMC Mode Registers (SMCMR n ) The two SMC mode registers (SMCMR), shown in Figure 29-2, select the SMC mode as well as mode-speciÞc parameters.
Page 780 Common SMC Settings and Conﬁgurations Table 29-1. SMCMR Field Descriptions (Continued) Bits Name Description Stop length. (UART) 0 One stop bit. 1 Two stop bits. — Reserved, should be cleared (transparent) Monitor enable. (GCI) 0 The SMC does not support the monitor channel. 1 The SMC supports the monitor channel.
Page 781 Common SMC Settings and Conﬁgurations Dual-Port RAM External Memory TxBD Table Status and Control Data Length SMC TxBD Table Buffer Pointer Tx Data Buffer RxBD Table Status and Control SMC RxBD Table Data Length Buffer Pointer Rx Data Buffer Pointer to SMCx RxBD Table Pointer to SMCx TxBD Table...
Page 782 Common SMC Settings and Conﬁgurations Table 29-2. SMC UART and Transparent Parameter RAM Memory Map Offset Name Width Description 0x00 RBASE Hword RxBDs and TxBDs base address. (BD table pointer) Deﬁne starting points in the dual-port RAM of the set of BDs for the SMC send and receive functions. They allow 0x02 TBASE Hword...
Page 783 Common SMC Settings and Conﬁgurations Table 29-2. SMC UART and Transparent Parameter RAM Memory Map (Continued) Offset Name Width Description 0x28 — Hword First half-word of protocol-speciﬁc area. 0x32 — Hword Last half-word of protocol-speciﬁc area. From SMC base address. SMC base = IMMR + 3E80 (SMC1), 3F80 (SMC2). Not accessed for normal operation.
Page 784 Common SMC Settings and Conﬁgurations 29.2.4 Disabling SMCs On-the-Fly An SMC can be disabled and reenabled later by ensuring that buffers are closed properly and new data is transferred to or from a new buffer. Such a sequence is required if the parameters to be changed are not dynamic.
Page 785 SMC in UART Mode 29.2.4.4 SMC Receiver Shortcut Sequence ÂThis shorter sequence reinitializes receive parameters to their state after reset. 1. Clear SMCMR[REN]. 2. Make any changes, then issue an command. INIT RX PARAMETERS 3. Set SMCMR[REN]. 29.2.4.5 Changing SMC Protocols To switch the protocol that the SMC is executing without resetting the board or affecting the other SMC, follow these steps: 1.
Page 786 SMC in UART Mode ¥ Interrupts on special control character reception ¥ Ability to transmit data on demand using the TODR ¥ SCCS register to determine idle status of the receive pin ¥ Other features for the SCC as described in the GSMR However, the SMC UART frame format, shown in Figure 29-5, allows a data length of up to 14 bits.
Page 787 SMC in UART Mode Table 29-4. SMC UART-Specific Parameter RAM Memory Map Offset Name Width Description 0x28 MAX_IDL Hword Maximum idle characters. When a character is received on the line, the SMC starts counting idle characters received. If MAX_IDL idle characters arrive before the next character, an idle time-out occurs and the buffer closes, which sends an interrupt request to the core to receive data from the buffer.
Page 788 SMC in UART Mode 29.3.4 SMC UART Channel Reception Process When the core enables the SMC receiver, it enters mode and waits for the Þrst HUNT character. The CP then checks the Þrst RxBD to see if it is empty and starts storing characters in the buffer.
Page 789 SMC in UART Mode Table 29-5. Transmit Commands (Continued) Command Description Enables characters to be sent on the transmit channel. The SMC UART controller expects it after RESTART disabling the channel in its SMCMR and after issuing the command. The SMC UART TRANSMIT STOP TRANSMIT controller resumes transmission from the current TBPTR in the channel’s TxBD table.
Page 790 SMC in UART Mode Table 29-7. SMC UART Errors Error Description Overrun The SMC maintains a two-character length FIFO for receiving data. Data is moved to the buffer after the ﬁrst character is received into the FIFO; if a receiver FIFO overrun occurs, the channel writes the received character into the internal FIFO.
Page 791 SMC in UART Mode Table 29-8 describes SMC UART RxBD status and control Þelds. Table 29-8. SMC UART RxBD Status and Control Field Descriptions Name Description Empty. 0 The buffer is full or data reception stopped due to an error. The core can read or write any ﬁelds of this RxBD.
Page 792 SMC in UART Mode MRBLR = 8 Bytes for this SMC Receive BD 0 Buffer Status Byte 1 Length 0008 Byte 2 Buffer Full Pointer 32-Bit Buffer Pointer 8 Bytes etc. Byte 8 Receive BD 1 Buffer Status Byte 9 Length 0002 Byte 10...
Page 793 SMC in UART Mode 29.3.11 SMC UART Transmit BD (TxBD) Data is sent to the CPM for transmission on an SMC channel by arranging it in buffers referenced by descriptors in the channelÕs TxBD table. Using the BDs, the CP confirms transmission or indicates error conditions so that the processor knows the buffers have been serviced.
Page 794 SMC in UART Mode 8-bit data, 1 start, and 1 stop, initialize the data length Þeld to 3. To send three UART characters of 9-bit data, 1 start, and 1 stop, the data length Þeld should 6, because the three 9-bit data Þelds occupy three half words in memory (the 9 LSBs of each half word).
Page 795 SMC in UART Mode Figure 29-10 shows an example of the timing of various events in the SMCE. Characters Received by SMC UART 10 Characters Time Line Idle Line Idle Break SMC UART SMCE BRKE Events NOTES: 1. The first RX event assumes receive buffers are 6 bytes each. 2.
Page 796 SMC in Transparent Mode 10. Clear BRKLN and BRKEC in the SMC UART-speciÞc parameter RAM. 11. Set BRKCR to 0x0001; if a is issued, one break STOP TRANSMIT COMMAND character is sent. 12. Initialize the RxBD. Assume the Rx buffer is at 0x0000_1000 in main memory. Write 0xB000 to Rx_BD_Status, 0x0000 to Rx_BD_Length (not required), and 0x0000_1000 to Rx_BD_Pointer.
Page 797 SMC in Transparent Mode 29.4.1 SMC Transparent Mode Features The following list summarizes the features of the SMC in transparent mode: ¥ Flexible buffers ¥ Can connect to a TDM bus using the TSA in the SI ¥ Can transmit and receive transparently on its own set of pins using a sync pin to synchronize the beginning of transmission and reception to an external event ¥...
Page 798 SMC in Transparent Mode 29.4.4 SMC Transparent Channel Reception Process When the core enables the SMC receiver in transparent mode, it waits for synchronization before receiving data. Once synchronization is achieved, the receiver transfers the incoming data into memory according to the Þrst RxBD in the table. Synchronization can be achieved in two ways.
Page 799 SMC in Transparent Mode Note that regardless of whether the transmitter or receiver uses SMSYN, it must make glitch-free transitions from high-to-low or low-to-high. Glitches on SMSYN can cause erratic behavior of the SMC. The transmitter and receiver never lose synchronization again, regardless of the state of SMSYN, until the TEN bit is cleared or an command is issued.
Page 800 SMC in Transparent Mode SMSYN. Chapter 20, ÒSerial Interface,Ó describes how to conÞgure time slots. The TSA allows the SMC receiver and transmitter to be enabled simultaneously and synchronized separately; SMSYN does not provide this capability. Figure 29-12 shows synchronization using the TSA.
Page 801 SMC in Transparent Mode When the transmit FIFO is loaded, synchronization and transmission begins depending on the following: ¥ If a buffer is made ready before the SMC is enabled, the Þrst byte is placed in time slot 1 if CLEN is 8 and to slot 2 if CLEN is greater than 8. ¥...
Page 802 SMC in Transparent Mode Table 29-12. SMC Transparent Receive Commands (Continued) Command Description Forces the SMC to close the current receive BD if it in use and to use the next BD in the list for CLOSE RXBD subsequent received data. If the SMC is not in the process of receiving data, no action is taken. Initializes receive parameters in this serial channel to reset state.
Page 803 SMC in Transparent Mode Table 29-14 describes SMC transparent RxBD Þelds. Table 29-14. SMC Transparent RxBD Field Descriptions Bits Name Description Empty. 0 The buffer is full or reception was aborted due to an error. The core can read or write any ﬁelds of this RxBD.
Page 804 SMC in Transparent Mode Table 29-15 describes SMC transparent TxBD Þelds. Table 29-15. SMC Transparent TxBD Field Descriptions Bits Name Description Ready. 0 The buffer is not ready for transmission. The BD and buffer can be updated. The CP clears R after the buffer is sent or after an error occurs.
Page 805 SMC in Transparent Mode 29.4.11 SMC Transparent Event Register (SMCE)/Mask Register (SMCM) The SMC event register (SMCE) generates interrupts and reports events recognized by the SMC channel. When an event is recognized, the SMC sets the corresponding SMCE bit. Interrupts are masked in the SMCM, which has the same format as the SMCE. SMCE bits are cleared by writing ones;...
Page 806 SMC in Transparent Mode 2. ConÞgure the port A pins to enable CLK3. Set PAPAR[5] and clear PADIR[5]. The other pin functions are the timers or the TSA. These alternate functions cannot be used on this pin. 3. Connect CLK3 to SMC1 using the SI. Clear SIMODE[SMC1] and set SIMODE[SMC1CS] to 0b110.
Page 807 SMC in GCI Mode 1. Write RBASE and TBASE in the SMC parameter RAM to point to the RxBD and TxBD in the dual-port RAM. Assuming one RxBD at the beginning of the dual-port RAM followed by one TxBD, write RBASE with 0x0000 and TBASE with 0x0008. 2.
Page 808 SMC in GCI Mode 29.5.1 SMC GCI Parameter RAM The SMC GCI parameter RAM area begins at the same offset from each SMC base. The parameter RAM differs from that for UART and transparent mode. In GCI mode, parameter RAM contains both the BDs and their buffers. Compare Table 29-17 with Table 29-2 to see the differences.
Page 809 SMC in GCI Mode 29.5.3 Handling the GCI C/I Channel The C/I channel is used to control the OSI layer 1 device. The OSI layer 2 device in the TE sends commands and receives indication to or from the upstream layer 1 device through C/I channel 0.
Page 810 SMC in GCI Mode Table 29-19 describes SMC monitor channel RxBD Þelds. Table 29-19. SMC Monitor Channel RxBD Field Descriptions Bits Name Description Empty. 0 The CP clears E when the byte associated with this BD is available to the core. 1 The core sets E when the byte associated with this BD has been read.
Page 811 SMC in GCI Mode 29.5.7 SMC GCI C/I Channel RxBD The GCI C/I channel RxBD, shown in Figure 29-18, is used by the CP to report on the C/I channel receive byte. The RxBD itself receives the C/I data. Offset + 0 —...
Page 812 SMC in GCI Mode 29.5.9 SMC GCI Event Register (SMCE)/Mask Register (SMCM) The SMCE generates interrupts and reports events recognized by the SMC channel. When an event is recognized, the SMC sets its corresponding SMCE bit. SMCE bits are cleared by writing ones;...
Page 813 Chapter 30 Serial Peripheral Interface (SPI) The serial peripheral interface (SPI) allows the MPC857T to exchange data between other MPC857T chips, the MC68360, the MC68302, the M68HC11 and M68HC05 microcontroller families, and peripheral devices such as EEPROMs, real-time clocks, A/D converters, and ISDN devices.
Page 814 Features 30.1 Features The following is a list of the SPIÕs main features: ¥ Four-signal interface (SPIMOSI, SPIMISO, SPICLK, and SPISEL) ¥ Full-duplex operation ¥ Works with data characters from 4 to 16 bits long ¥ Supports back-to-back character transmission and reception ¥...
Page 815 Conﬁguring the SPI Controller ¥ When the SPI is a master, SPICLK is the clock output signal that shifts received data in from SPIMISO and transmitted data out to SPIMOSI. SPI masters must output a slave select signal to enable SPI slave devices by using a separate general-purpose I/O signal.
Page 816 Conﬁguring the SPI Controller MPC857T Slave 0 SPIMOSI SPIMOSI SPIMISO SPIMISO SPICLK SPICLK SPISEL Master SPI Slave 1 SPIMOSI SPIMISO The SPISEL SPICLK decoder can be SPISEL either internal or external logic. Slave 2 SPIMOSI SPIMISO SPICLK SPISEL Figure 30-2. Single-Master/Multi-Slave Configuration To start exchanging data, the core writes the data to be sent into a buffer, conÞgures a TxBD with TxBD[R] set, and conÞgures one or more RxBDs.
Page 817 Conﬁguring the SPI Controller 30.3.2 The SPI as a Slave Device In slave mode, the SPI receives messages from an SPI master and sends a simultaneous reply. The slaveÕs SPISEL must be asserted before Rx clocks are recognized; once SPISEL is asserted, SPICLK becomes an input from the master to the slave.
Page 818 Conﬁguring the SPI Controller MPC857T SPI #0 SPIMOSI SPIMISO SPICLK SPISEL SELOUT1 SELOUT2 SELOUT3 MPC857T SPI #1 SPIMOSI SPIMISO SPICLK SPISEL SELOUT0 SELOUT2 SELOUT3 MPC857T SPI #2 SPIMOSI SPIMISO SPICLK SPISEL SELOUT0 SELOUT1 SELOUT3 MPC857T SPI #3 SPIMOSI SPIMISO SPICLK SPISEL SELOUT0 SELOUT1...
Page 819 SPI Registers 30.4 SPI Registers The following sections describe the registers used in conÞguring and operating the SPI. 30.4.1 SPI Mode Register (SPMODE) The SPI mode register (SPMODE), shown in Figure 30-4, controls both the SPI operation mode and clock source. Field —...
Page 820 SPI Registers Table 30-1. SPMODE Field Descriptions (Continued) Bits Name Description 8–11 Character length in bits per character. Must be between 0011 (4 bits) and 1111 (16 bits). A value less than 4 causes erratic behavior. If the value is not greater than a byte, every byte in memory holds LEN valid bits.
Page 821 SPI Registers 30.4.1.2 SPI Examples with Different SPMODE[LEN] Values The examples below show how SPMODE[LEN] is used to determine character length. To help map the process, the conventions shown in Table 30-2 are used in the examples. Table 30-2. Example Conventions Convention Description –...
Page 822 SPI Registers 30.4.2 SPI Event/Mask Registers (SPIE/SPIM) The SPI event register (SPIE) generates interrupts and reports events recognized by the SPI. When an event is recognized, the SPI sets the corresponding SPIE bit. Clear SPIE bits by writing a 1Ñwriting 0 has no effect. Setting a bit in the SPI mask register (SPIM) enables and clearing a bit masks the corresponding interrupt.
Page 823 SPI Parameter RAM Table 30-4 describes the SPCOM Þelds. Table 30-4. SPCOM Field Descriptions Bits Name Description Start transmit. For an SPI master, setting STR causes the SPI to start transferring data to and from the Tx/Rx buffers if they are prepared. For a slave, setting STR when the SPI is idle causes it to load the Tx data register from the SPI Tx buffer and start sending with the next SPICLK after SPISEL is asserted.
Page 824 SPI Parameter RAM Table 30-5. SPI Parameter RAM Memory Map (Continued) Offset Name Width Description 0x10 RBPTR Hword RxBD pointer. Points to the current Rx BD being processed or to the next BD to be serviced when idle. After a reset or when the end of the BD table is reached, the CPM initializes RBPTR to the RBASE value.
Page 825 SPI Commands Table 30-6. RFCR/TFCR Field Descriptions Bits Name Description 0– — Reserved, should be cleared. 3–4 Byte ordering. Set BO to select the required byte ordering for the buffer. If BO is changed on-the-ﬂy, it takes effect at the beginning of the next frame or BD. See Appendix A, “Byte Ordering.” 00 Reserved 01 PowerPC little-endian.
Page 826 The SPI Buffer Descriptor (BD) Table Dual-Port RAM External Memory TxBD Table Tx Buffer Frame Status Data Length Tx Buffer Buffer Pointer Pointer to SPI TxBD Table RxBD Table Pointer to SPI Rx Buffer Frame Status RxBD Table Data Length Buffer Pointer Figure 30-10.
Page 827 The SPI Buffer Descriptor (BD) Table 30.7.1.1 SPI Receive BD (RxBD) The CPM uses RxBDs to report on each received buffer. It closes the current buffer, generates a maskable interrupt, and starts receiving data in the next buffer once the current buffer is full.
Page 828 The SPI Buffer Descriptor (BD) Table Table 30-8. SPI RxBD Status and Control Field Descriptions (Continued) Bits Name Description Overrun. Set when a receiver overrun occurs during reception (slave mode only). The SPI updates OV after the received data is placed in the buffer. Multimaster error.
Page 829 SPI Master Programming Example Table 30-9. SPI TxBD Status and Control Field Descriptions (Continued) Bits Name Description 7–13 — Reserved, should be cleared. Underrun. Indicates that the SPI encountered a transmitter underrun condition while sending the buffer. This error occurs only when the SPI is in slave mode. The SPI updates UN after it sends the buffer.
Page 830 SPI Slave Programming Example 13. Write 0x0370 to SPMODE to enable normal operation (not loopback), master mode, SPI enabled, 8-bit characters, and the fastest speed possible. 14. Clear PBDAT[156], assuming PB156 is chosen above, to constantly assert the SPI select output signal. 15.
Page 831 Handling Interrupts in the SPI 30.10 Handling Interrupts in the SPI The following sequence should be followed to handle interrupts in the SPI: 1. Once an interrupt occurs, read SPIE to determine the interrupt source. Normally, SPIE bits should be cleared at this time. 2.
Page 832 Handling Interrupts in the SPI 30-20 MPC857T PowerQUICC User’s Manual...
Page 833 Chapter 31 C Controller The inter-integrated circuit (I C¨) controller lets the MPC857T exchange data with other C devices, such as microcontrollers, EEPROMs, real-time clock devices, A/D converters, and LCD displays. The I C controller uses a synchronous, multimaster bus that can connect several integrated circuits on a board.
Page 834 I2C Features The I C receiver and transmitter are double-buffered, which corresponds to an effective two-character FIFO latency. In normal operation, the msb (bit 0) is shifted out Þrst. When the I C is not enabled in the I C mode register (I2MOD[EN] = 0), it consumes little power. 31.1 I C Features The following is a list of the I...
Page 835 I2C Controller Transfers 31.3 I C Controller Transfers To initiate a transfer, the master I C controller sends a message specifying a read or write request to an I C slave. The Þrst byte of the message consists of a 7-bit slave port address and a R/W request bit.
Page 836 I2C Controller Transfers Data Byte Device Address Note: Data and ACK are repeated n times. Figure 31-4. I C Master Write Timing A master write performed by the MPC857T occurs as follows: 1. Set the masterÕs I2COM[STR]. The transfer starts when the SDMA channel loads the transmit FIFO with data and the I C bus is not busy.
Page 837 I2C Controller Transfers Device Address Data Byte Note: After the nth data byte, the master does not acknowledge the slave. Figure 31-5. I C Master Read Timing A master read performed by the MPC857T occurs as follows: 1. Set the masterÕs I2COM[STR] to initiate the read. The transfer starts when the SDMA channel loads the transmit FIFO with data and the I C bus is not busy.
Page 838 I2C Registers An MPC857T I C controller attempting a master read request could simultaneously be targeted for an external master write (slave read). Both operations trigger the controllerÕs I2CER[RXB] event, but only one operation wins the bus arbitration. To determine which operation caused the interrupt, software must verify that its transmit operation actually completed before assuming that the received data is the result of its read operation.
Page 839 I2C Registers Table 31-1. I2MOD Field Descriptions (Continued) Bits Name Description 5–6 PDIV Predivider. Selects the clock division factor before it is input into the I C BRG. The clock source for the C BRG is the BRGCLK generated by the SIU. 00 BRGCLK/32 01 BRGCLK/16 10 BRGCLK/8...
Page 840 I2C Registers Table 31-3. I2BRG Field Descriptions Bits Name Description 0–7 Division ratio 0–7. Speciﬁes the divide ratio of the BRG divider in the I C clock generator. The output of the prescaler is divided by 2 * ([DIV0–DIV7] + 3) and the clock has a 50% duty cycle. DIV must be programmed to a minimum value of 3 if the digital ﬁlter is disabled and 6 if it is enabled.
Page 841 I2C Parameter RAM Field — Reset 0000_0000 Addr 0x86C Figure 31-10. I C Command Register (I2COM) Table 31-5 describes I2COM Þelds. Table 31-5. I2COM Field Descriptions Bits Name Description Start transmit. In master mode, setting STR causes the I C controller to start sending data from the C Tx buffers if they are ready.
Page 842 I2C Parameter RAM Table 31-6. I C Parameter RAM Memory Map (Continued) Offset Name Width Description 0x06 MRBLR Hword Maximum receive buffer length. Deﬁnes the maximum number of bytes the I C receiver writes to a receive buffer before moving to the next buffer. The receiver writes fewer bytes to the buffer than the MRBLR value if an error or end-of-frame occurs.
Page 843 I2C Commands Table 31-7 describes the RFCR/TFCR bit Þelds. Table 31-7. RFCR/TFCR Field Descriptions Bits Name Description 0–2 — Reserved, should be cleared. 3–4 Byte ordering. Set BO to select the required byte ordering for the buffer. If BO is changed on-the-ﬂy, it takes effect at the beginning of the next frame (Ethernet, HDLC, and transparent) or at the beginning of the next BD.
Page 844 I2C Buffer Descriptor (BD) Tables Dual-Port RAM External Memory TxBD Table Tx Buffer Status and Control Data Length Tx Buffer Buffer Pointer C TxBD Table C RxBD Table RxBD Table Rx Buffer Status and Control Data Length C RxBD Table Pointer (RBASE) Buffer Pointer C TxBD Table Pointer...
Page 845 I2C Buffer Descriptor (BD) Tables Offset + 0 — — — Offset + 2 Data Length Offset + 4 RX Buffer Pointer Offset + 6 Figure 31-13. I C Receive Buffer Descriptor (RxBD) Table 31-9 describes I C RxBD status and control bits. Table 31-9.
Page 846 I2C Buffer Descriptor (BD) Tables Offset + 0 — — Offset + 2 Data Length Offset + 4 Tx Buffer Pointer Offset + 6 Figure 31-14. I C Transmit Buffer Descriptor (TxBD) Table 31-10 describes I C TxBD status and control bits. Table 31-10.
Page 847 Chapter 32 Parallel Interface Port (PIP) Multiplexed through the 18-bit port B parallel I/O, the parallel interface port (PIP) allows data to be sent to and from the MPC857T over 8 or 16 parallel data lines with two handshake control signals. The PIP signals are grouped into two sets, PB[24Ð31] and PB[14Ð23], allowing the PIP to be conÞgured as an 8- or 16-bit port.
Page 848 Core Control vs. CP Control Figure 32-1 is a block diagram of the PIP. U-Bus Peripheral Bus PIP Configuration Register (PIPC) Timing Parameters Register (PTPR) PIP Data Register Port B Data Direction (PBDIR) Port B Pin Assignment Register (PBPAR) Handshake Port B Open Drain Register (PBODR) Control PIP Event Register (PIPE)
Page 849 The PIP Parameter RAM 32.2.2 CP Control When the PIP is controlled by the CP (PIPC[HSC] = 0), any of the three handshake modes can be used. Data is prepared by the core using PIP buffer descriptors. CP-controlled strobed transfers are the same as core-controlled transfers described above, except reads and writes to PBDAT are done automatically by DMA.
Page 850 The PIP Parameter RAM Table 32-1. PIP Transmitter Parameter RAM Memory Map (Continued) Offset Name Width Description 0x22 T_CNT Hword Tx internal byte count. 0x24 TTEMP Word Tx temporary. From PIP base address. PIP base = IMMR + 0x3F80 (SMC2) 32.3.1.1 PIP Function Code Register (PFCR) Figure 32-2 shows the PIP function code register (PFCR).
Page 851 The PIP Parameter RAM If the core controls the transmitter, the masking function can be performed in software by reading the individual status signals for errors. When receiving, core software drives the status signals using general-purpose outputs. Field Addr PIP base + 0x05 Figure 32-3.
Page 852 The PIP Parameter RAM Table 32-4. PIP Receiver Parameter RAM Memory Map (Continued) Offset Name Width Description 0x08 RSTATE Word Rx internal state. 0x0C R_PTR Word Rx internal data pointer. 0x10 RBPTR Hword RxBD pointer. Points to the current Rx BD being processed or to the next BD to be serviced when idle.
Page 853 The PIP Parameter RAM Offset 0x2C — CHARACTER1 0x2E — CHARACTER2 • • • • • • • • • • • • • • • 0x3A — CHARACTER8 0x3C — RCCM 0x3E — RCCR From PIP base address Figure 32-4. Control Character Table, RCCM, and RCCR Table 32-5 describes the control character table, RCCM, and RCCR Þelds.
Page 854 The PIP Registers 32.4 The PIP Registers The PIP registers include one conÞguration register (PIPC), and an event register (PIPE) with its corresponding mask register (PIPM). A timing parameters register (PTPR) allows the user to program pulsed handshake timings. The port B registers must also be conÞgured for PIP operation.
Page 855 The PIP Registers Table 32-6. PIPC Field Descriptions (Continued) Bits Name Description 8–9 TMOD Timing mode. Used to implement a Centronics-type receiver. Valid only when T/R = 0 (Rx operation) and MODH = 11 (pulsed handshake). For the deﬁnition of these timing modes, see Section 32.7.2.2, “Pulsed Handshake Timing.”...
Page 856 The PIP Registers Table 32-7 describes PIPE Þelds. Table 32-7. PIPE Field Descriptions Bits Name Description 0–2 — Reserved. Should be cleared by writing ones. Transmit error. Indicates a general transmit error—the source of the speciﬁc error can be read in the current buffer descriptor’s status and control ﬁeld;...
Page 857 PIP Buffer Descriptors 32.4.5 The Port B Registers The PIP uses parallel I/O port B. Figure 32-8 shows the basic operation of port B. U-Bus Read from U-Bus Write from U-Bus Buffer Latch DIR = Output Figure 32-8. Port B General-Purpose I/O The following describes the conÞguration of the port B registers for PIP operation;...
Page 858 PIP Buffer Descriptors ¥ The word at offset + 4 points to the beginning of the buffer. Ñ For an RxBD, the value must be even and can reside in internal or external memory. Ñ For a TxBD, this pointer can be even or odd, unless the port size exceeds 8 bits, for which it must be even.
Page 859 PIP Buffer Descriptors Table 32-9. PIP TxBD Status and Control Field Descriptions (Continued) Bits Name Description Fault. 0 The FAULT status line has remained negated during transmission. 1 The FAULT status line has been asserted during transmission. Paper error. 0 The PERROR status line has remained negated during transmission. 1 The PERROR status line has been asserted during transmission.
Page 860 PIP CP Commands Table 32-10. PIP RxBD Status and Control Field Descriptions (Continued) Bits Name Description Control character 0 This buffer does not contain a control character. 1 This buffer has a user-deﬁned control character as its last byte. — Reserved and should be cleared.
Page 861 Handshaking I/O Modes 32.7 Handshaking I/O Modes In either handshaking I/O mode, interlocked or pulsed, the PIP can be conÞgured as a transmitter or receiver and either the CP or the core can control communications. For CP control, BD and parameter RAM initialization is required; data is stored in the buffers using the SDMA channels dedicated to SMC2.
Page 862 Handshaking I/O Modes 32.7.2 Pulsed Handshake Mode The pulsed handshake mode, shown in Figure 32-12, supports a Centronics-compatible interface. Peripheral Bus Read from CP Write from CP Latch Latch Write from Handshake DIR = Output Control Logic (DIR = OUT) CP/Core In Use Tx Data...
Page 863 Handshaking I/O Modes 32.7.2.1 The BUSY Signal In pulsed handshake mode, the PIP receiver can generate an additional BUSY handshake signal that is useful when implementing a Centronics receiver interface. The BUSY output is used to indicate a transfer in progress; the PIP receiver asserts BUSY as soon as data is latched into the PIP data register.
Page 864 Handshaking I/O Modes Data TPAR1 TPAR2 Figure 32-14. PIP Transmitter Timing Diagram A PIP receiver in pulsed handshake mode has four options for determining the relative timing of BUSY to ACK. Figure 32-15 through Figure 32-18 show how the deÞnitions of TPAR1 and TPAR2 vary for each receiver mode.
Page 865 Transparent Transfers BUSY Cleared BUSY by S/W (PB31) TPAR1 TPAR2 Figure 32-18. PIP Receiver Timing—Mode 3 32.8 Transparent Transfers The timing of transparent transfers, shown in Figure 32-19, is controlled by the timing of the strobe signal STBI (PB14). Transparent transfers must be controlled by the CP, which requires BD and parameter RAM initialization.
Page 866 Implementing Centronics Traditionally, Centronics transfers have been one-way from the host to a peripheral device, but new standards like IEEE P1284 allow bidirectional transfers. With software to allow switching between receive and transmit modes, the PIP can support bidirectional transfers, but does not fully comply with the full-duplex P1284 standard interface.
Page 867 Implementing Centronics For each transfer, the PIP drives the data on the Centronics interface data lines and generates a strobe pulse, assuming the previous data has been acknowledged and the minimum setup time requirement is met. Strobe pulse width and setup time parameters are set in the PIP timing parameters register (PTPR).
Page 868 Implementing Centronics 32.9.2 PIP as a Centronics Receiver If the current BD in the RxBD table is empty and a character is received from the Centronics interface, the PIP receiver Þrst compares the character against the user-deÞned control character table. If no match is found, the character is written to the buffer. If a match is found, the control character is either written to the Rx buffer or rejected, depending on the reject bit in the control character table.
Page 869 Implementing Centronics Chapter 32. Parallel Interface Port (PIP) 32-23...
Page 870 Implementing Centronics 32-24 MPC857T PowerQUICC User’s Manual...
Page 871 Chapter 33 Parallel I/O Ports The CPM supports four general-purpose I/O portsÑA, B, C, and D. Each signal in the I/O ports can be conÞgured as a general-purpose I/O signal or as a signal dedicated to supporting communications devices, such as SMCs and SCC1. ¥...
Page 872 Features 33.1 Features The following lists the main features of the parallel I/O ports: ¥ Port A is 16 bits ¥ Port B is 18 bits. Port B is shared with the PIP, which is described in Chapter 32, ÒParallel Interface Port (PIP).Ó ¥...
Page 873 Port A Table 33-1. Port A Pin Assignment (Continued) Pin Function Signal PAPAR[DD n ] = 1 PAPAR[DD n ] = 0 Input to On-Chip Peripherals (General I/O) (Default) PADIR[DR n ] = 0 PADIR[DR n ] = 1 PORT A4 CLK4 TOUT2 CLK4 = CLK8...
Page 874 Port A Table 33-2 describes PAODR bits. Table 33-2. PAODR Bit Descriptions Bits Name Description 0–7, 13, 15 — Reserved, always reads as 0. 8–12, 14 Tells how the corresponding port A signal is interpreted. 0 The signal is actively driven as an output. 1 The signal is an open-drain driver.
Page 875 Port A Table 33-4 describes PADIR bits. Table 33-4. PADIR Bit Descriptions Bits Description 0–15 Port A data direction. Conﬁgures port A signals as inputs or outputs when functioning as general-purpose I/O; otherwise, used to select the peripheral function. 0 Select the signal for general-purpose input, or select peripheral function 0. 1 Select the signal for general-purpose output, or select peripheral function 1.
Page 876 Port A ¥ PA14 can be conÞgured as a general-purpose I/O signal, either open-drain or not. See Section 33.2.3, ÒPort A Functional Block Diagrams.Ó Ñ If PA14 is conÞgured as a general-purpose I/O signal, the TXD1 output is not connected externally. If SCC1 is connected to a TDM or is not used, PA14 can be used for general-purpose I/O.
Page 877 Port A Using PA14 as an example, Figure 33-6 shows the functional block diagram for all port A signals with open-drain capability. Read Path To PADAT[14] Write Path From RXD1/PA14 PADAT[14] Open Drain Output Control Latch 16-Bits PADIR 16-Bits TXD1 From SCC1 PAODR 16-Bits...
Page 878 Port B 33.3 Port B All port B signals can be open-drain. They are conÞgured independently as general-purpose I/O signals if the corresponding bit in the PBPAR is cleared and they are conÞgured as dedicated on-chip peripheral signals if the corresponding PBPAR bit is set. When conÞgured as a general-purpose I/O signal, the signal direction of that signal is determined by the corresponding control bit in the PBDIR.
Page 879 Port B Table 33-6. Port B Pin Assignment (Continued) Signal Function Signal PBPAR[DD n ] = 1 Input to On-chip Peripherals PBPAR[DD n ] = 0 (Default) PBDIR[DR n ] = 0 PBDIR[DR n ] = 1 PB23 Port B23 SMSYN1 SDACK1 SMSYN1 = GND...
Page 880 Port B Field — Reset 0000_0000_0000_0000 — Addr 0xAC0 Field OD16 OD17 OD18 OD19 0D20 0D21 OD22 OD23 OD24 OD25 OD26 OD27 OD28 OD29 OD30 OD31 Reset Addr 0xAC2 Figure 33-7. Port B Open-Drain Register (PBODR) Table 33-8 describes PBODR bits. Table 33-8.
Page 881 Port B Table 33-9 describes PBDAT bits. Table 33-9. PBDAT Bit Descriptions Bits Name Description 0–13 — Reserved 14–31 Contains the data on the corresponding signal. 33.3.2.3 Port B Data Direction Register (PBDIR) Port B data direction register (PBDIR) bits conÞgure port B signals as general-purpose inputs or outputs.
Page 882 Port C Bits Field — DD14 DD15 Reset — — — — — — — — — — — — — — — Addr 0xABC Bits Field DD16 DD17 DD18 DD19 DD20 DD21 DD22 DD23 DD24 DD25 DD26 DD27 DD28 DD29 DD30 DD31 Reset Addr 0xABE...
Page 883 Port C Table 33-12. Port C Pin Assignment PCPAR[DD n ] = 0 PCPAR[DD n ] = 1 Input to On-Chip Signals Peripherals PCDIR[DR n ] = 1 PCDIR[DR n ] = 0 PCDIR[DR n ] = 0 PCDIR[DR n ] = 1 (Default) or PCSO[ n ] = 0 and PCSO[ n ] = 1...
Page 884 Port C 3. Write the corresponding PCSO bit with a zero. 4. The corresponding PCINT bit is a ÔdonÕt careÕ bit. 5. Write the corresponding CIMR bit with a zero to prevent interrupts from being generated to the core. 6. Read the signal value using the PCDAT register. When a port C signal is conÞgured as a general-purpose I/O input, a change in the port C interrupt register (PCINT) causes an interrupt request signal to be sent to the CPIC.
Page 885 Port C PC14 can be programmed to assert special requests directly to the CPM by setting RCCR[EIE]; however, do not do so unless instructed by a Motorola-supplied RAM microcode package. For IDMA, PC14 can be programmed to function as external DMA request (DREQx) signals.
Page 886 Port C Table 33-14 describes PCDAT bits. Table 33-14. PCDAT Bit Descriptions Bits Name Description 0–3 — Reserved 4–15 Contains the data on the corresponding signal. 33.4.2.2 Port C Data Direction Register (PCDIR) Port C data direction register (PCDIR) bits conÞgure port C signals as general-purpose inputs or outputs.
Page 887 Port C Table 33-16 describes PCPAR bits. Table 33-16. PCPAR Bit Descriptions Bits Name Description 0–3 — Reserved. 4–15 Conﬁgures a signal for general-purpose I/O or for dedicated peripheral function 0 General-purpose I/O. The peripheral functions of the signal are not used. 1 Dedicated peripheral function.
Page 888 Port D 33.4.2.5 Port C Interrupt Control Register (PCINT) Each bit of the port C interrupt control (PCINT) register, shown in Figure 33-15, corresponds to a port C signal to determine whether that line asserts an interrupt request on a high-to-low transition or on any transition. PCINT is cleared by reset. Field —...
Page 889 Port D Table 33-19. Port D Pin Assignment (Continued) PORT D9 PORT D8 — — PORT D7 — — PORT D6 — — PORT D5 — PORT D4 — PORT D3 — Specialized versions of the multiplex the port D signals with other functions, such as an ATM UTOPIA interface or 100BASE-T MII (media-independent interface).
Page 890 Port D 33.5.1.2 Port D Data Direction Register (PDDIR) The port D data direction register (PDDIR) provides bits for specifying whether port D signals are inputs or outputs when functioning as general-purpose I/O. Field — DR3 DR4 DR5 DR6 DR7 DR8 DR9 DR10 DR11 DR12 DR13 DR14 DR15 Reset 0000_0000_0000_0000 Addr...
Page 891 Port D Port D signals are conÞgured as follows in the port D pin assignment register (PDPAR): ¥ General-purpose I/O signal (the corresponding PDPAR[DDn] = 0) ¥ Dedicated on-chip peripheral signal (PDPAR[DDn] = 1) PDPAR and the port D data direction register (PDDIR) are cleared at reset, thus conÞguring all port D signals as general-purpose input signals.
Page 892 Port D 33.5.2.1 Port D Data Register A read of the port D data (PDDAT) register returns the value of the signal, regardless of whether it is an input or output. This allows output conßicts to be found on the signal by comparing the written data with the data on the signal.
Page 893 Port D The Þelds in the PDPAR register are described in Table 33-25. Table 33-25. PDPAR Field Descriptions Bits Name Description ATM global enable. 0 =Disable ATM SAR functionality 1 =Enable ATM SAR functionality UTOPIA enable. Determines whether the parameter RAM’s page 4 (SCC4) operates in serial or UTOPIA mode.
Page 894 Port D 33.5.4.2 Port D Data Direction Register (PDDIR) The port D data direction register (PDDIR) provides bits for specifying whether port D signals are inputs or outputs when functioning as general-purpose I/O. Field — DR3 DR4 DR5 DR6 DR7 DR8 DR9 DR10 DR11 DR12 DR13 DR14 DR15 Reset 0000_0000_0000_0000 Addr...
Page 895 Port D ¥ General-purpose I/O signal (the corresponding PDPAR[DDn] = 0) ¥ Dedicated on-chip peripheral signal (PDPAR[DDn] = 1) PDPAR and the port D data direction register (PDDIR) are cleared at reset, thus conÞguring all port D signals as general-purpose input signals. Chapter 33.
Page 896 Port D 33-26 MPC857T PowerQUICC User’s Manual...
Page 897 Chapter 34 CPM Interrupt Controller The CPM interrupt controller (CPIC) accepts and prioritizes the internal and external interrupt requests from the CPM blocks and passes them to the system interface unit (SIU). The CPIC also provides a vector during the core interrupt acknowledge cycle. 34.1 Features The following is a list of the CPICÕs main features: ¥...
Page 898 CPM Interrupt Source Priorities System Interface Unit (SIU) Software Watchdog Timer Communications Processor Module (CPM) Generator IRQ[0:7] IRQ0 Edge/ Level System Reset Interrupt Port C[4:15] Decrementer Decrementer Level 7 CPM Timer[1–4] SCC[1] Level 6 Timebase PowerPC SMC[1–2] Core Level 5 Periodic Interrupt Level 4...
Page 899 CPM Interrupt Source Priorities Table 34-1. Prioritization of CPM Interrupt Sources Multiple Multiple Priority Source Description Priority Source Description Events Events 0x1F Parallel I/O–PC15 0x0F Parallel I/O–PC11 (Highest) 0x1E 0x0E Parallel I/O–PC10 0x1D 0x0D 0x1C 0x0C Timer3 0x1B 0x0B Parallel I/O–PC9 0x1A Parallel I/O–PC14 0x0A...
Page 900 Masking Interrupt Sources in the CPM The CPM interrupt in-service register (CISR) can be used to allow a higher priority interrupt within the same interrupt level to be presented to the core before a lower priority interrupt service completes. Each CISR bit corresponds to a CPM interrupt source. When the core acknowledges the interrupt by setting IACK, the CPIC sets the CISR bit for that interrupt source.
Page 901 Generating and Calculating Interrupt Vectors The following procedure prevents possible interrupt errors when modifying mask registers, such as the CIMR, SCCM, SMCM, or any other CPM interrupt mask: 1. Clear MSR[EE]. (Disable external interrupts to the core.) 2. Modify the mask register. 3.
Page 902 CPIC Registers The table is the same as the CPM interrupt priority table (Table 34-1) except that the SCC vector number is Þxed. Also the last entry in this table is the error vector, which the CPM issues if it requested an interrupt that the user cleared before the core serviced it and no other interrupts for the CPM are pending.
Page 903 CPIC Registers CICR bits are described in Table 34-3. Table 34-3. CICR Field Descriptions Bits Name Description 0–15 — Reserved, should be cleared. 16–18 IRL Interrupt request level. Contains the priority request level of the interrupt from the CPM that is sent to the SIU.
Page 904 CPIC Registers In a polled interrupt scheme, the user must periodically read the CIPR. To avoid losing subsequent events from the same interrupt source, acknowledge an interrupt before actually handling it in the service routine. Acknowledge interrupts from port C by clearing the CIPR bit directly (by writing ones).
Page 905 Interrupt Handler Example—Single-Event Interrupt Source 34.5.5 CPM Interrupt Vector Register (CIVR) The CPM interrupt vector register (CIVR) is used to identify an interrupt source. The core uses the IACK bit to acknowledge an interrupt. CIVR can be read at any time. Field IACK Reset...
Page 906 Interrupt Handler Example—Multiple-Event Interrupt Source 34.7 Interrupt Handler Example—Multiple-Event Interrupt Source In this example, CIPR[SCC1] remains set as long as one or more event bits remain unmasked in SCCE1. This is an example of a handler for an interrupt source with multiple events.
Page 907 Part VI Asynchronous Transfer Mode (ATM) Intended Audience Part VI is intended for system designers who need to use the MPC857T asynchronous transfer mode capabilities. It assumes a basic understanding of the PowerPC exception model, the MPC857T interrupt structure, the MPC857T communications processor module (CPM) with a particular emphasis on the SCC, as well a working knowledge of ATM.
Page 908 ¥ Chapter 39, ÒATM Pace Control,Ó describes how the ATM pace control unit (APC) processes trafÞc parameters of each channel and deÞnes the multiplex timing for all the channels. ¥ Chapter 40, ÒATM Exceptions,Ó describes how the circular ATM interrupt queue operates with an event register (SCCE or IDSR1) to provide an interrupt model for ATM operations.
Page 909 Table vii. Acronyms and Abbreviated Terms Term Meaning ATM adaptation layer AAL5 CPCS–PDU Available bit rate Allowed cell rate Arithmetic logic unit ATM pace control Asynchronous transfer mode Buffer descriptor Bit interleaved parity BIST Built-in self test Backward reporting cells Burst tolerance Constant bit rate Content-addressable memory...
Page 910 Table vii. Acronyms and Abbreviated Terms (Continued) Term Meaning EEST Enhanced Ethernet serial transceiver EPROM Erasable programmable read-only memory ESAR Enhanced segmentation and reassembly Free buffer pool FIFO First-in-ﬁrst-out (buffer) Forward monitor cells Forward resource management General circuit interface GCRA Generic cell rate algorithm (leaky bucket) Generic ﬂow control GPCM...
Page 911 Table vii. Acronyms and Abbreviated Terms (Continued) Term Meaning Not a number NCITS Number of cells in a time slot Network interface card Network interface unit NMSI Nonmultiplexed serial interface Non-real time Open systems interconnection Peripheral component interconnect Protocol data unit Peak cell rate Physical layer Performance monitors...
Page 912 Table vii. Acronyms and Abbreviated Terms (Continued) Term Meaning SRTS Synchronous residual time stamp Transmit connection table Time-division multiplexed Terminal endpoint of an ISDN connection Translation lookaside buffer Time-slot assigner Transmit Unspeciﬁed bit rate UBR+ Unspeciﬁed bit rate with minimum cell rate guarantee UART Universal asynchronous receiver/transmitter User-programmable machine...
Page 913 Chapter 35 ATM Overview The MPC857T provides enhanced ATM functionality over that of the MPC860SAR. The MPC857T adds major new features available in Òenhanced SARÓ (ESAR) mode, including the following: ¥ Multiple APC priority levels available to support a range of trafÞc pace requirements ¥...
Page 914 Using UTOPIA and Fast Ethernet 35.2.1 Parameter RAM Conﬂicts Operating serial ATM on SCC1 or the UTOPIA interface causes other peripherals to lose their parameter RAM. For SCC1, the serial ATM parameters extend into the I C parameter RAM default location. However, the parameters for I C can be relocated without the need for RAM-based microcode.
Page 915 Using UTOPIA and Fast Ethernet UTOPIA Only Pin Resources Pin Resources PCMCIA PCMCIA Port A RxData PCMCIA Port A TxData Port D TxData Port D RxData UTOPIA Muxed Bus UTOPIA Master Split Bus Fast Ethernet Only Pin Resources Pin Resources PCMCIA PCMCIA Port A PCMCIA Port A...
Page 916 ATM Features 35.4 ATM Features The MPC857T supports the following features: ¥ Serial ATM capability on the SCC ¥ Optional UTOPIA port ¥ Simultaneous MII (100Base-T) and UTOPIA operation when operating the UTOPIA port in muxed bus mode ¥ Cell processing up to 96 Mbps aggregate receive and transmit via UTOPIA interface (with 80 MHz system clock) ¥...
Page 917 ATM Features Ñ Segmentation: Ð Segments CPCS_PDU directly from host memory Ð Performs CPCS_PDU padding Ð CRC32 generation Ð Automatic last cell marking (in the PTI Þeld of the cell header) Ð Automatic CS_UU, CPI, and LENGTH insertion (in the last cell of the frame) ¥...
Page 918 MPC857T Application Example ¥ ATM pace control (APC) unit: Ñ Pace controller Ð Constant bit rate (CBR) service on a per VC basis Ð UnspeciÞed bit rate (UBR) pacing Ð Available bit rate (ABR) pacing (pace is managed by upper-layer host software when establishing a connection) ¥...
Page 919 Overview of ATM Operation 35.6 Overview of ATM Operation The MPC857T supports ATM adaptation layers AAL0 and AAL5 segmentation and reassembly and the ATM layer for the convergence sublayer (CS). User data resides in system memory in single or multiple data buffers. There are two physical layer/interface modes of operation: a UTOPIA interface and a serial interface.
Page 920 UTOPIA Operation the cell header entry of the TCT, and sends the complete cell through the UTOPIA interface. For the last cell of an AAL5 frame, the transmitter appends the trailer of the common part conversion sublayer-protocol data unit (CPCS-PDU) to the user frame. It pads as required, appends the length (calculated during the frame transmit), and copies the CPCS-UU and CPI from the TxBD.
Page 921 Serial ATM Operation The CRC10 option is used to support OAM cell checking (by host software) according to the ITU speciÞcation I.610. Note that the received HEC is not checked by the ATM controller in UTOPIA mode; it is the responsibility of the PHY to check the HEC and discard cells with an incorrect HEC. 35.7.3 Expanded Cells An option for supporting ATM cells larger than the standard 53 bytes (4-byte header, 1-byte HEC and 48-byte payload) is available when operating in UTOPIA mode.
Page 922 Serial ATM Operation 35.8.1 Serial ATM Transmit Overview The serial transmit process begins with the APC. The APC controls the ATM trafÞc of the transmitter through a user-conÞgured timer that deÞnes the maximum outgoing bit rate. The APC uses each ATM channelÕs speciÞc trafÞc parameters to divide the total bit rate among the active channels.
Page 923 Serial ATM Operation As the FIFO of the SCC Þlls, the received cell is read from the FIFO, the HEC is checked, and the cell is optionally descrambled. Cells with HEC errors are passed to the global raw cell queue, and the HEC error is recorded in the BD. The receiver screens out either idle cells or unassigned cells as programmed.
Page 924 ATM Pace Control (APC) 35.9 ATM Pace Control (APC) The ATM pace controller determines the next channel (or n channels) to be transmitted and writes the channel number of these channels in the transmit queue every APC slot time. The transmitter sends one cell for each channel entry in the transmit queue.
Page 925 ATM Port-to-Port (PTP) Cell Switching The TCTs and RCTs for internal channels are directly accessed in the (internal) dual-port RAM. For external channels, the TCT and RCT structures are placed in external memory and thus require DMA accesses to read and update. Also, the GFC/VPI/VCI/PTI mapping for external channels requires a CAM or address compression method instead of the generally faster dual-port RAM look-up table method used for internal channels.
Page 926 General ATM Initialization Requirement ¥ For reassembly operations, stored ATM-PDUs can be transmitted in AAL0 mode, looped back and reassembled as AAL5 CPCS-PDUs by converting each sequence of received ATM-PDU in AAL5 mode. 35.13 General ATM Initialization Requirement All ATM parameter RAM areas and data structures, such as the connection tables and APC priority levels, should be cleared before beginning the actual system initialization process.
Page 927 Chapter 36 Buffer Descriptors and Connection Tables The communications processor module (CPM) manages ATM trafÞc through the UTOPIA and serial interfaces by means of transmit and receive buffer descriptors (BDs) and transmit and receive connection tables (TCTs and RCTs). The BDs are grouped into circular tables of pointers into the data buffer space in external memory.
Page 928 ATM Buffer Descriptors (BDs) BD Memory Space (up to 256 KByte) Buffer Memory Space (4 Gbyte) Pointer from TBD_BASE Parameter RAM Tx BD Table of Ch1 Tx Buffer1 of TBASE Tx BD 1 Channel1 Pointers from Tx BD 2 Ch1 TCT Tx BD 3 Tx Buffer3 of TBD_PTR...
Page 929 ATM Buffer Descriptors (BDs) 36.1.2 AAL0 Buffers AAL0 buffers contain one raw cell. When the receiver or transmitter completes writing or reading the buffer, it moves to the next BD in the AAL0 channelÕs BD table in preparation for the next transfer and optionally issues an interrupt. AAL0 buffers are 64 bytes.
Page 930 ATM Buffer Descriptors (BDs) For UTOPIA operation, a global option to support expanded cells is available. ATM RxBDs in expanded cell mode are 24 bytes, as shown in Figure 36-4. OFFSET + 0 — Ñ — — OFFSET + 2 DATA LENGTH/CHANNEL CODE OFFSET + 4 RX DATA BUFFER POINTER...
Page 931 ATM Buffer Descriptors (BDs) Table 36-1. ATM RxBD Field Descriptions Offset from Bits Name Description RBD_PTR 0x00 Empty. Determines whether a buffer is accessible by the CPU core or the CP. 0 The data buffer associated with this RxBD has been ﬁlled with the received data, or data reception has been aborted due to an error condition.
Page 932 ATM Buffer Descriptors (BDs) Table 36-1. ATM RxBD Field Descriptions (Continued) Offset from Bits Name Description RBD_PTR 0x00 Continuous mode. Note that RxBD[E] is cleared if an error occurs during reception, regardless of CM. 0 Normal operation. 1 RxBD[E] is not cleared by the CPM after this BD is closed, allowing the associated buffer to be overwritten next time the CPM accesses it.
Page 933 ATM Buffer Descriptors (BDs) Table 36-1. ATM RxBD Field Descriptions (Continued) Offset from Bits Name Description RBD_PTR 0x08 — CPCS-UU CPCS-UU and CPI (AAL5 only). Contains the frame’s CPCS-UU and CPI and CPI ﬁelds. This ﬁeld is taken from the frame trailer, and contains user-to-user (UU) information and common part indications (CPI).
Page 934 ATM Buffer Descriptors (BDs) OFFSET + 14 CELL HEADER EXPANSION 3 Figure 36-6. ATM TxBD in Expanded Cell Mode (UTOPIA Only) Table 36-2 describes the ATM TxBD Þelds. Table 36-2. ATM TxBD Field Descriptions Offset from Bits Name Description TBD_PTR 0x00 Ready.
Page 935 ATM Buffer Descriptors (BDs) Table 36-2. ATM TxBD Field Descriptions (Continued) Offset from Bits Name Description TBD_PTR Replace header (AAL5 only). Valid only when the current BD is the ﬁrst BD of an AAL5 frame. The RH mechanism allows the dynamic modiﬁcation of the channel’s ATM cell header per frame.
Page 936 Receive and Transmit Connection Tables (RCTs and TCTs) 36.2 Receive and Transmit Connection Tables (RCTs and TCTs) The receive and transmit connection tables (RCTs and TCTs) hold conÞguration and control information and temporary parameters for each receive and transmit ATM channel. Although the transmit and receive sections of the same channel number are independent of each other, their RCTs and TCTs are paired together in connection tables (CTs).
Page 937 Receive and Transmit Connection Tables (RCTs and TCTs) CNG/ CNGI / CT_Offset + 0 FHNT — — — — — — — CDIS NCRC CT_Offset + 2 RBALEN CT_Offset + 4 RCRC CT_Offset + 6 CT_Offset + 8 RB_PTR CT_Offset + A CT_Offset + C RTMLEN CT_Offset + E...
Page 938 Receive and Transmit Connection Tables (RCTs and TCTs) Table 36-3. RCT Field Descriptions (Continued) CT Offset Bits Name Description CNG/NCRC CNG—Congestion (AAL5 only). Used internally by the CP, RCT[CNG] indicates that congestion has been reported in the last cell of the current frame. RCT[CNG] is set only if the last cell of the current AAL5 frame has arrived with the PTI[EFCI] bit set in its header.
Page 939 Receive and Transmit Connection Tables (RCTs and TCTs) Table 36-3. RCT Field Descriptions (Continued) CT Offset Bits Name Description 0x08 — RB_PTR Receive buffer pointer. This ﬁeld is valid only when INF is set. RB_PTR is the physical address of the current buffer location to which data is being written. Should be cleared during initialization.
Page 940 Receive and Transmit Connection Tables (RCTs and TCTs) CT_Offset + 0 FHNT — NCRC — CDIS — CT_Offset + 2 WCOUNT CT_Offset + 4 PTP_TX_CH CT_Offset + 6 — — — AVCO SCC# — — — CT_Offset + 8 ADDRESS TRANSLATION HEADER CT_Offset + A CT_Offset + C APC_LEVEL...
Page 941 Receive and Transmit Connection Tables (RCTs and TCTs) Table 36-4. PTP RCT Field Descriptions (Continued) CT Offset Bits Name Description 0x02 — WCOUNT Wrap count. Counts the number of BD table wraps. The CP increments WCOUNT on every BD table wrap and approximates the total cell count, where: WCOUNT*table_size <...
Page 942 Receive and Transmit Connection Tables (RCTs and TCTs) Table 36-4. PTP RCT Field Descriptions (Continued) CT Offset Bits Name Description 0x0C APC_LEVEL Contains the base address of the APC priority level used to transfer the channel. For single PHY mode: 1st priority: APC_LEVEL = APCPTR 2nd priority: APC_LEVEL = APCPTR + (1 x 32) 3rd priority: APC_LEVEL = APCPTR + (2 x 32)
Page 943 Receive and Transmit Connection Tables (RCTs and TCTs) CT_Offset + 20 — — — — — — — — — — — CR10 CDIS CT_Offset + 22 TBALEN CT_Offset + 24 TCRC CT_Offset + 28 TB_PTR CT_Offset + 2C TTMLEN CT_Offset + 2E TBD_PTR CT_Offset + 30...
Page 944 Receive and Transmit Connection Tables (RCTs and TCTs) Table 36-5. TCT Field Descriptions (Continued) CT Offset Bits Name Description 0x24 — TCRC Temporary CRC32 (AAL5 only). CP scratch pad area for the CRC32 calculation. 0x28 — TB_PTR Transmit buffer pointer. Contains the real address of the current data position in the transmit buffer.
Page 945 Receive and Transmit Connection Tables (RCTs and TCTs) Table 36-5. TCT Field Descriptions (Continued) CT Offset Bits Name Description 0x3A — APCPR APC pace remainder. Contains the remainder of the rate generated by the APC after adding the pace FRACTION to the cumulative APCPR. Should be cleared during initialization.
Page 946 Receive and Transmit Connection Tables (RCTs and TCTs) CT_Offset + 20 — — — — — — — — — — — CR10 CDIS — CT_Offset + 22 — CT_Offset + 34 — CT_Offset + 28 — CT_Offset + 2C —...
Page 947 Receive and Transmit Connection Tables (RCTs and TCTs) Table 36-6. PTP TCT Field Descriptions (Continued) CT Offset Bits Name Description 0x2E — PTP_BD_PTR PTP BD pointer. Points to the current BD in the PTP BD table. The actual address of the current BD is (PTP_BD_PTR x 4) + TBDBASE (where TBDBASE is the base pointer to the TxBD memory space).
Page 948 Receive and Transmit Connection Tables (RCTs and TCTs) Table 36-6. PTP TCT Field Descriptions (Continued) CT Offset Bits Name Description 0x3C APC out. Can be used as a completion ﬂag for the TRANSMIT DEACTIVATE CHANNEL command. When the command is issued, OUT is TRANSMIT DEACTIVATE CHANNEL immediately set.
Page 949 Receive and Transmit Connection Tables (RCTs and TCTs) Dual-port RAM External Memory ETCTEBASE Reserved in (Located in the TCTE (Internal Use) Extended Channel 32 x 32 Bytes Parameter RAM) Mode of User Space TCTEBASE (Located in the TCTE0 Parameter RAM) TCTE32 TCTE1 —...
Page 950 Receive and Transmit Connection Tables (RCTs and TCTs) 36-24 MPC857T PowerQUICC User’s Manual...
Page 951 Chapter 37 ATM Parameter RAM The SCC parameter RAM is used to conÞgure the SCC for serial ATM and the UTOPIA interface. The CP also uses parameter RAM to store operational and temporary values used during SAR activities. When ATM operations are performed, the SCC parameter RAM is mapped as shown in Table 37-1, Table 37-2, and Table 37-3.
Page 952 Table 37-1. Serial ATM and UTOPIA Interface Parameter RAM Map (Continued) Offset Name Width Description 0x14 TBDBASE Word Base pointer for all TxBD tables. Deﬁnes the starting location in external memory of up to 256 Kbytes in which the TxBD tables for all connections are located.
Page 953 Table 37-1. Serial ATM and UTOPIA Interface Parameter RAM Map (Continued) Offset Name Width Description 0x3C OLDLEN Hword Transmitter temporary length. Do not write to this location. 0x3E SMRBLR Hword SAR maximum receive buffer length register. Determines the number of bytes the CP writes to a receive buffer before moving to the next buffer.
Page 954 Table 37-1. Serial ATM and UTOPIA Interface Parameter RAM Map (Continued) Offset Name Width Description 0x54 Hword Address match parameters 1–5. The ATM controller provides three methods for address matching: using a lookup table, address compression, or 0x56 Hword content-addressable memory (CAM). See Section 37.5, “Address Match Parameters (AM1–AM5),”...
Page 955 Table 37-1. Serial ATM and UTOPIA Interface Parameter RAM Map (Continued) Offset Name Width Description 0x74 — 12 Bytes Reserved 0x7F Notes: Parameters shown shaded are used for serial ATM only. Non-shaded parameters are used for both serial ATM and UTOPIA operations. Parameters shown in boldface type must be initialized by the user before enabling ATM operations.
Page 956 SAR Receive Function Code Register (SRFCR) Table 37-3 describes additional parameters needed to conÞgure the SCC for serial ATM operation. Table 37-3. Serial ATM Parameter RAM Map Offset Name Width Description 0xC0 ALPHA Hword Receiver delineation alpha/delta counters. The ATM controller applies the HEC delineation mechanism described in ITU speciﬁcation I.432 0xC2 DELTA...
Page 957 SAR Receive State Register (SRSTATE) user-initialized function codes and byte ordering information for DMA transfers. FIELD — RESET — — — — — — — — OPER Figure 37-1. SAR Receive Function Code Register (SRFCR) The SRFCR Þelds are described in Table 37-4. Table 37-4.
Page 958 SAR Transmit Function Code Register (STFCR) Table 37-5. SRSTATE Field Descriptions Bits Name Description Extended channel mode. EXT and ACP select the address matching mechanism; see Section 37.5, “Address Match Parameters (AM1–AM5).” 0 Maximum of 31.5 channels available. (Receive channel 0 is reserved for the raw cell queue.) Channel mapping and connection tables are supported internally.
Page 959 SAR Transmit State Register (STSTATE) The STFCR Þelds are described in Table 37-6. Table 37-6. STFCR Field Descriptions Bits Name Description 0–2 — Reserved 3–4 Byte ordering. Program BO to select the required byte ordering for the SDMA transfers. 00 Reserved 01 PowerPC little-endian.
Page 960 Address Match Parameters (AM1–AM5) Table 37-7. STSTATE Field Descriptions (Continued) Bits Name Description ATM physical interface type 0 UTOPIA PHY 1 Serial PHY. — Reserved and should be cleared. 37.5 Address Match Parameters (AM1–AM5) The ATM controller uses one of the three following methods for address matching. ¥...
Page 961 Address Match Parameters (AM1–AM5) Table 37-8. AM1–AM5 Parameters for the Internal Look-up Table Field Name Function HMASK Header mask. The ATM controller masks the header of each incoming cell with HMASK and uses the resulting masked header in the address match process. The masking process uses a bitwise AND function so bits are masked out by clearing the relevant bits in HMASK.
Page 962 Address Match Parameters (AM1–AM5) Table 37-10. AM1–AM5 Parameters for Extended Channel Address Compression Field Name Function FLBASE First-level table base. Contains the word-aligned starting address for the ﬁrst-level table of the address compression mechanism. SLBASE Second-level table base. Pointer to the beginning of a 64-Kbyte memory space where the set of second-level addressing tables are located.
Page 963 APC State Register (APCST) Table 37-12. AM1–AM5 Parameters for Extended Channel CAM Operation Field Name Function HMASK Header mask. The ATM controller masks the header of each incoming cell with HMASK and uses the resulting masked header for address matching. The masking process uses a bitwise AND function so bits are masked out by clearing the relevant bits in HMASK.
Page 964 Serial Cell Synchronization Status Register (ASTATUS) Table 37-13. APCST Field Descriptions (Continued) Bit(s) Name Description 5–7 NMPHY Reserved in ESAR mode. (Classic SAR only) Number of (multiple) PHYs. Valid only for the SCC4 parameter RAM when in UTOPIA multi-PHY mode; in all other parameter RAM pages (SCC1–3), this ﬁeld should be cleared.
Page 965 Serial Cell Synchronization Status Register (ASTATUS) The ASTATUS Þelds are described inTable 37-14. Table 37-14. ASTATUS Register Field Descriptions Bits Name Description 0–5 — Reserved ORUN Receiver FIFO overrun. The CP sets this ﬂag to indicate a receiver overrun event has occurred. The user can acknowledge the ﬂag by clearing it.
Page 966 Serial Cell Synchronization Status Register (ASTATUS) 37-16 MPC857T PowerQUICC User’s Manual...
Page 967 Chapter 38 ATM Controller This chapter describes the address mapping mechanisms of the ATM controller to support connection tables for single-PHY interfaces, and the commands provided to control ATM transmit and receive operations on a channel-by-channel basis. 38.1 Address Mapping Three methods for mapping incoming cell header addresses to local ATM channel numbers are available.
Page 968 Address Mapping address matching algorithm reaches the bottom of the table (AMBASE) without a match, the incoming cell is directed to the global raw cell queue; that is, the base address of RCT0 should be placed in the corresponding last entry of the pointing table (APBASE). Note that the internal look-up mechanism searches the address matching table sequentially from the top (AMEND) to the base (AMBASE).
Page 969 Address Mapping FLMASK to create a pointer (offset from FLBASE) to the Þrst-level addressing table. The Þrst-level table (FLT) contains an additional mask and table pointer to one of the second-level tables (SLTs), referred to as the second-level table offset (SLTOFFSET). (SLTOFFSET is an offset from the base address of the second-level tables (SLBASE).
Page 970 Address Mapping 38.1.2.3 Address Compression Example Figure 38-2 shows an example of address compression. The Þrst-level mask (FLMASK) selects the third PTI bit and Þve VPI bits. Bitwise ANDing of the FLMASK with the GFC, VPI, and PTI bits results in a 6-bit pointer. Pointer1 turns out to equal 0x3, and therefore is pointing to the fourth entry of the FLT.
Page 971 Port-to-Port (PTP) Switching Note that if CUMB is set, the user should also include the PTI bits in FLMASK so that cells marked as congested (EFCI = 1) or last (PTI[1] =1) in the PTI are not received into the global raw cell queue.
Page 972 Port-to-Port (PTP) Switching MPC857T RxBD Table Tx Queue scheduling Activated table Host channel TxBD Table TxBD Table UTOPIA BYPASS Figure 38-3. Host-controlled Switching Serial ATM to a UTOPIA Channel In contrast, the PTP switching mechanism does cell switching automatically. The cell is received directly into the buffers of a common PTP BD table shared by the receive channel and the transmit channel associated with the PTP connection.
Page 973 Port-to-Port (PTP) Switching 38.2.2 PTP Buffers PTP buffers follow the AAL0 buffer structure. See Section 36.1.2, ÒAAL0 Buffers.Ó 38.2.3 PTP Buffer Descriptors The PTP BD, shown in Figure 38-5, is common to the receiver and transmitter. PTP BDs can be thought of as modiÞed TxBDs because they use the TxBD base pointers (TBDBASE in the parameter RAM and PTP TCT[PTP_BD_PTR,PTP_BASE]).
Page 974 Statistical Counters Table 38-1. PTP BD Field Descriptions (Continued) Offset from Bits Name Description PTP_BD_PTR 0x04 — PTP Buffer PTP (transmit/receive) buffer pointer. Points to the ﬁrst location of this BD’s Pointer data buffer, which may reside in either internal or external memory. This pointer must be burst aligned (divisible by 16).
Page 975 ATM Commands TotalRxCells TotalRxCLP1 0x10–0x1F — (Reserved) Figure 38-6. Statistics Table In serial ESAR mode, the counters are activated by programming the base pointer of the statistics table (STATBASE in the ESAR parameter RAMÑsee Table 37-2) to a non-zero value. In UTOPIA ESAR mode, set UTMODE[STAT] to activate the counters.
Page 976 ATM Commands Table 38-2. CPCR ATM-Specific Field Descriptions Bits Name Description CP reset command. Set by the core and cleared by the CP. Executing this command clears RST and FLG within two general system clocks. The CPM reset routine takes approximately 60 clocks, but CPM initialization can start immediately after this command is issued.
Page 977 ATM Commands The ATM commands are described in Table 38-3. Table 38-3. ATM Commands Command Description Opcode Activates the channel speciﬁed in COMM_CH by inserting its channel number into the TRANSMIT ACTIVATE APC scheduling table at the location indicated by the service pointer. The channel CHANNEL most recently inserted is the ﬁrst to be chosen by the APC.
Page 978 ATM Commands Table 38-3. ATM Commands Command Description Opcode Inserts the channel number speciﬁed in COMM_CH directly into the transmit queue. APC BYPASS Enables out-of-rate cell transmission with cell pacing determined by the user. Make sure that the combined bit rate of all transmitted channels (APC-scheduled, PTP-switched and out-of-rate channels) does not exceed the maximum allowed by the PHY.
Page 979 Chapter 39 ATM Pace Control The ATM layer performs cell multiplexing and demultiplexing. The ATM pace control unit (APC) is part of the ATM cell multiplexing process. The APC processes the trafÞc parameters of each channel and deÞnes the multiplex timing for all the channels. Cell multiplexing is done by the transmitter according to the trafÞc control function implemented by the APC.
Page 980 APC Algorithm Figure 39-1 shows the APC process and transmit ßow in UTOPIA mode. The APC obtains a channelÕs pacing information from its TCT so that it can be re-scheduled, and writes the channel number to the transmit queue. For AAL5 channels, the transmitter implements AAL and SAR functions on the external memory for the chosen channel.
Page 981 APC Algorithm APC Timer ATM port to port Request (timer expiration) (PTP) queueing APC control Priority Counter APC scheduling table level 1 Priority Counter APC scheduling table level 2 Priority Counter APC scheduling table level n PHY Transmit queue Transmitter Figure 39-2.
Page 982 APC Algorithm The entries of an APC scheduling table are actually the heads of linked lists. That is, if more than one channel is scheduled to the same time slot, the Þrst channel points to the next channel using the APC link Þeld (APCL) in its TCT, and so on. Having scheduled the channels at the current table entry (APCT_PTRx), the APC then inserts up to NCITS channel numbers into the transmit queue using the service pointer (APCT_SPTRx).
Page 983 APC Algorithm Trade-off decisions must be made when programming these parameters. The following subsections provide examples of the analysis required to make these determinations. 39.1.3 Programming APC Scheduling Table Size and NCITS The size of the APC scheduling table is deÞned by the minimum bit rate desired for a single connection and the number of cells transmitted in a time slot.
Page 984 APC Algorithm 39.1.4 Deﬁning APC Slot Time The APC deÞnes the maximum bit rate of the cell scheduler through the period of the APC timer tick and the number of cells scheduled per APC timer tick (NCITS). The period of the APC timer is referred to as an APC time slot.
Page 985 APC Algorithm For another example, assume the desired bit rate is 10Mbps. Then APC_Pace should be programmed to 51.84Mbps / (4 * 10Mbps) = 1.296. This can be approximated by programming APCP=1 and APCPF = 19399. Note that APC_Pace consists of an integer and a fraction. A channel with a non-integer APC_Pace will be scheduled such that its average pace will be as deÞned by APCP and APCPF.
Page 986 Direct Scheduling of Cells Furthermore, the APC scheduling table parameters must be initialized before any commands are issued. However, these commands may be TRANSMIT CHANNEL ACTIVATE issued at any time, whether the APC timer is active or inactive. For more information, see the description of the command.
Page 987 Using the APC with Multiple ATM Ports 39.3 Using the APC with Multiple ATM Ports The APC algorithm always begins in page 4 of the dual-port RAM. For applications running only a single serial ATM port (on SCC1), the page-4 APCST parameter should deÞne the APC of page 4 as ÔinactiveÕ...
Page 988 Using the APC Without Using UTOPIA 39.4 Using the APC Without Using UTOPIA As described in Section 39.3, ÒUsing the APC with Multiple ATM Ports,Ó the APC algorithm begins and terminates by referring to the APCST parameter on parameter page 4.
Page 989 PHY Transmit Queues First Priority Table Second Priority Table nth Priority Table APCT_BASE1 APCT_BASE2 APCT_BASE APCT_PTR APCT_PTR1 APCT_PTR2 APCT_END1 APCT_END2 APCT_END Half word Half word Half word Note: APCT_END points to one position after the last entry in the table Figure 39-4.
Page 990 APC Priority Levels A transmit queue never overßows because the TQAPTR pointer never wraps to point to the TQTPTR pointer. If the transmit queue is full, the APC does not insert more channels, and the APCT_SPTR stalls until space is available in the transmit queue. The depth of the transmit queue is equal to the number of entries minus 1.
Page 991 APC Priority Levels Table 39-1. APC Priority Levels (Continued) Offset Name Width Description User Writes (n * 0x20) + 0x0 APCT_BASEn Half Word APC scheduling table base pointer User deﬁned for the N’th priority APC level (n * 0x20) + 0x2 APCT_ENDn Half Word N’th table —Length...
Page 992 APC Priority Levels Table 39-2. APC Priority Level Parameter Descriptions (Continued) Name Description NCITS Number of cells in time slot. Parameter set by the user. It holds the number of cells which are transmitted in a time slot. This number can include fractions of a cell. The NCITS ﬁeld is deﬁned as follows: The NCITS bit ﬁelds are described below.
Page 993 APC Priority Levels Table 39-2. APC Priority Level Parameter Descriptions (Continued) Name Description EAPCSTn ESAR APC state (N’th level). Contains initialization control information for this APC priority level. 3 4 5 6 7 8 9 10 11 Field APCOM — LAST —...
Page 994 Combined APC and PTP Programming Example Table 39-2. APC Priority Level Parameter Descriptions (Continued) Name Description PTP_COUNTER Port-to-port cell counter. Indicates the number of cells in the APC PTP queue of this speciﬁc priority level. Used by the APC controller. The user should initialize this ﬁeld to 0. PTP_TxCh The local transmit channel number associated with the APC PTP queue of this speciﬁc APC level.
Page 995 APC Scheduling Flow of a higher priority than the APC scheduling table, APCO interrupts are masked at this level. Ñ address 0x23A: PTP_COUNTER=0x0000 - initialize the PTP counter Ñ address 0x23C: PTP_TxCh=0x0002 - channel 2 is the PTP transmitting channel of this priority level.
Page 996 APC Scheduling Flow Scheduling one channel from an APC level PTP_counter>0 Equal priority? (EQ=1) Read the channel# from the Schedule from the APC scheduling table APC PTP queue Insert PTP_Tx_ch# to the Read the channelÕs specific scheduling transmit queue parameters from the TCT and ETCT Decrement PTP_counter Remove the channel from the TCT[OUT] = 1?
Page 997 Chapter 40 ATM Exceptions Interrupt handling for ATM channels involves two principle data structures: an event register (SCCE or IDSR1) and a circular ATM interrupt queue. The interrupt queue (one per controller) is shown in Figure 40-1. 32 Bits INTBASE V = 0 W = 0 V = 0...
Page 998 ATM Event Registers After an interrupt request, the hostÕs interrupt service routine polls the controllersÕ event registers (SCCE[GINT] and/or IDSR1[GINT]) to determine which controller is requesting service. After clearing GINT, the host processes each valid queue entry in turn, clearing each V bit and all ßagged event bits so that the entry can be reused by the CP.
Page 999 ATM Event Registers Table 40-1. UTOPIA Event Register (IDSR1) Field Descriptions (Continued) Bits Name Description — Reserved Global receiver overrun. Indicates that an overrun occurred in the cell FIFO of the UTOPIA slave receiver. This overrun occurs only if an external UTOPIA master attempts to write a cell to the MPC857T by asserting RxEnb while the internal FIFO is not ready (RxClav is not asserted).
Page 1000 Interrupt Queue Entry Table 40-2. Serial ATM Event Register (SCCE) Field Descriptions (Continued) Bits Name Description Global transmitter underrun. Indicates that an underrun occurred in the SCC’s transmitter FIFO. A GUN error is fatal because the affected channels are unknown. After GUN is set, the transmitter stops data transmission from all channels and sets the APC disabled status ﬂag APCST[DIS].