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Memory Array; Address Multiplexer - HP 13255 Manual

Memory controller module
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13255
Memory Controller
13255-91252/07
REV JUN-23-81
3.3
MEMORY ARRAY
3.3.1
3.3.2
3.3.3
3.4
3.4.1
3.4.2
3.4.3
The memory array
consists of up to thirty-two 64K RAMS.
socketed to allow field upgrade and repair.
The RAMs are
The power distribution is via a low impedance 4-layer PC
board struc-
ture.
The
ceramic
capacitors which supply the transient current are
organized such that some redundancy exists.
This allows reliable oper-
ation with one open circuit component.
The memory array is organized as four modules of equal size (if all are
loaded).
The entire array is activated by the start of a memory cycle,
which is
when U71-9 goes low.
At that time,
a row address strobe is
sent to all
four banks.
The column address
s"i;robe passes through
a
four to
one decoder which determines which module is selected for read
or write.
ADDRESS MULTIPLEXER
The
address multiplexer
consists of two 74LS258 quad inverting 2 to
1
line tri-state multiplexers (U75,76) and a 74LS244 octal tri-state buf-
fer (U55).
The 74LS258 multiplexers select the row or column address from the ter-
minal bus address lines for memory cycles.
Which address is selected
is determined by R/C (delay line R12-2).
These multiplexers are put in
the
hi-Z state during refresh cycles and during power on (when refresh
is occuring continuously).
The
function
of the 74LS244 buffer is to either transfer or block the
re.fresh
address counter outputs from the
internal address bus.
This
buffer is enabled whenever refresh cycles are occuring
(i.e.
refresh
cycle or power on).

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