The memory array
consists of up to thirty-two 64K RAMS.
socketed to allow field upgrade and repair.
The RAMs are
The power distribution is via a low impedance 4-layer PC
capacitors which supply the transient current are
organized such that some redundancy exists.
This allows reliable oper-
ation with one open circuit component.
The memory array is organized as four modules of equal size (if all are
The entire array is activated by the start of a memory cycle,
when U71-9 goes low.
At that time,
a row address strobe is
sent to all
The column address
s"i;robe passes through
one decoder which determines which module is selected for read
consists of two 74LS258 quad inverting 2 to
line tri-state multiplexers (U75,76) and a 74LS244 octal tri-state buf-
The 74LS258 multiplexers select the row or column address from the ter-
minal bus address lines for memory cycles.
Which address is selected
is determined by R/C (delay line R12-2).
These multiplexers are put in
hi-Z state during refresh cycles and during power on (when refresh
is occuring continuously).
of the 74LS244 buffer is to either transfer or block the
address counter outputs from the
internal address bus.
buffer is enabled whenever refresh cycles are occuring
cycle or power on).