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HP 13255 Manual page 7

Memory controller module
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13255
Memory Controller
Table 5.0
Connector Information (cont)
13255-91252/05
Rev
JUN-23-81
-----------------------------------------------.---------------------------------
-----------------------------
--------------------------------------------------
Connector
I
and Pin
No.1
-------------
-------------
P1, Pin A
-B
-C
-D
-E
-F
-H
-J
-K
-L
-M
-N
-p
-R
-S
-T
-u
-v
-W
-x
-y
-z
Signal
Name
--------------
--------------
GND
PON
BUS 0
BUS 1
BUS 2
BUS 3
BUS
4
BUS 5
BUS
6
BUS 7
WRITE
WAIT
ADDR16
ADDR17
ADDR18
REQ
Signal
Description
-------------------------------------------------
-------------------------------------------------
Ground Common Return (Power and Signal)
Not Used
Not Used
Positive True, System Power On
Negative True, Data Bus Bit 0
Negative True, Data Bus Bit 1
Negative True, Data Bus Bit 2
Negative True, Data Bus Bit 3
Negative True, Data Bus Bit
4
Negative True, Data Bus Bit 5
Negative True, Data Bus Bit 6
Negative True, Data Bus Bit 7
Negative True, Write/Read
Type
Cycle
Not Used
Negative True, Assert Wait State
Not Used
Not Used
Positive True, Address Bit 16
Positive True, Address Bit 17
Positive True, Address Bit 18
Negative True, Request (Bus Data Valid)
Not Used
-------------------------------------------------------------------------------
--------------------------------------------------------------------------------

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