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HP 13255 Manual page 13

Memory controller module
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13255
Memory Controller
13255-91252/11
REV JUN-23-81
3.8.4
The board select circuitry combines the state of two of the three most
significant bus address lines, ADDR16 and ADDR18, as follows:
Table 6.0
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
ADDR18
ADDR17
ADDR16
FUNCTION
0
0
0
Code Page 0
0
0
1
Unused
0
1
0
Code Page 1
0
1
1
Unused
1
0
0
RAM Space for Variables
1
0
1
Unused
1
1
0
RAM for BASIC Workspace
1
1
1
Display/IO Space
-------------------------------------------------------------------------------
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3.8.5
As can be seen from the above table, a RAM-based terminal would have to
respond to all four cases where ADDR16=0; a ROM-based terminal needs to
respond to the two cases where ADDR18 and ADDR16 =10 .
When jumper W1 is
absent, the output of the
AND
gate (U14-6) passes the inverted value of
ADDR18.
This gets combined with the value of ADDR16 to generate MEMGO
(U42-6).
It is also combined with
10
to generate BOARD SELECT (053-6)
which is used to enable the
data port and to enable the row and column
address strobes to the memory array.
When W1 is present,
u14-5
is tied to ground,
therefore the output of
the AND gate (U14-6) is permanently low.
In this case, MEMGO and BOARD
SELECT depend only on the value of ADDR16.

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