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HP 13255 Manual page 11

Memory controller module
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13255
Memory Controller
13255-91252/09
REV JUN-23-81
3.6.2
The refresh timer consists of a 74LS393 dual four bit counter (U22) set
up as a divide by 64.
The output of this counter is synchronized with
the falling edge of the system clock to avoid collisions between memory
and refresh cycles (the memory cycle is synchronized to the rising edge
of the system clock by the
processor board).
This synchronization is
accomplished by use of a 74s74 flip flop
(U71).
The synchronized out-
put
(U71-6)
feeds the
preset input of another 74s74 flip flop
(052)
which acts as a refresh pending latch.
The output
of this flip flop
(U52-5) is ANDed with the signal HEM BUSY (U52-8)
which indicates if a
memory cycle
is previously in progress.
The positive true output of
this gate (014-8) is the signal RFSH, which indicates an active refresh
cycle in progress.
3.7
REFRESH CYCLE GENERATOR
3.7.1
3.7.2
The :refresh cycle generator generates a row address strobe which is fed
to the memory chips along with the refresh address;
the combination of
these signals performs a RAS only refresh cycle for the memory array.
The cycle is triggered by the
signal RFSH,
inverted and presented to
the clock input of a
74LS112 J-K flip flop
(U26).
This flip flop is
tied
to a
permanent set
state.
Setting this flip flop causes the K
input of the other half of u26 to go high resulting in the toggle state
at the inputs of this flip flop (U26-2,3).
The next rising edge of the
clock causes signal RFSH RAS to go low;
it will
remain so for one en-
tire clock cycle (204 nsec).
Two 74LS74 D flip flops
(013,23)
extend
the refresh cycle by one more complete clock cycle to
allow sufficient
RAS pre charge and address setup time as
discussed above.
U23-5 feeds
bac:k to the refresh timer to end the cycle and allow a new timing cycle
to begin.
During power on, the signal RESET forces u26 to the toggle state perma-
nently,
resulting in continuous refreshing until RESET returns to the
high state.

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