HP 13255 Manual page 8

13255
Memory Controller
13255-91252/06
Rev JUN-23-81
3.0 FUNCTIONAL DESCRIPTION. Refer to the block diagram (figure 1),
schematic diagram (figure 2 and 3), the timing diagram (figure 4), and
the parts list (02640-60252).
The Memory Controller Module provides program and variable space for
the terminal. It consists of memory drivers and series termination
resistors, data port, memory array, address multiplexer, refresh
address generator, refresh timer, refresh cycle generator, bus
interface and board select circuitry, and a memory cycle generator.
3.1 SERIES TERMINATION RESISTORS
The series termination resistors m1n1m1ze undershoot by terminating the
bus lines with the line impedance. This approximates to 20 ohms since
it consists of an 80 ohm line with distributed, lumped, and capacitive
lo~ds. Current limit protection is provided free which limits the
driver output to 75
mA
if two or more array inputs are shorted
together.
3.2 DATA PORT
3.2.1
3.2.2
The data port consists of a 74LS244 data in driver (U46) and a 74LS373
data out transparent latch. This port is enabled whenever BOARD SELECT
(U53-6) and REQ (P1-Y) are both low, causing U56-3 to go low. The
direction of data flow is arbitrated by WRITE (P1-P) in the following
manner: if WRITE is high, then U56-8 will
be
active, resulting in data
transmission from the Memory Controller to the data bus. If WRITE is
low, then U56-6 will
be
active, and the data flow will
be
from the bus
to the memory array. Data is latched in the output latch by the trail-
ing edge of CAS, the COllunn address strobe.
The transparent data latch (U27) allows data to propagate through the
latch prior to being latched. This means the RAM access time is
optimized and if a higher speed RAM is used, the memory will appear to
be correspondingly higher in speed. The data is latched so that
completion of the memory cycle does not depend on the completion of the
processor memory handshake.