MEMORY CYCLE GENERATOR
is a synchronous
composed of several flip flops and gates.
purpose of this state
generate the row and column address strobes for
cycle operations with the appropriate timing.
cycle begins when HEMGO goes low.
This is synchronized with
the leading edge of REQ by a 74s74 flip flop
This also accom-
plishes the rising edge
clock synchronization mentioned above in sec-
as REQ is synchronized with
the clock by
The output of this flip flop (071-9) represents a memory cycle pending.
This signal is ANDed with RFSH to
prevent a memory cycle from starting
refresh cycle is in progress.
The output of this gate(Ul5-6)
indicates an active memory cycle.
(negative) edge of this
cycle active signal
sets HEM BUSY to the true state,
start of any refresh
it also clocks
which starts MEMRAS,
the row address strobe
Two flip flops
(U13 and U25)
then maintain HEMRAS in the low state for 2 clock cycles
The output of the second flip flop
is the column
address strobe, CAS.
It lasts for one clock cycle
(204 nsec) and fol-
lows the leading edge of HEMRAS by 204 nsec subject to logic delays.
with the refresh cycle generator,
two 74LS74 D flip flops (U21) are
used to extend the memory cycle to allow for
pre charge time.
output of the second of these
state, thus ending the memory cycle.
MEMRAS is ted to a delay line (HP part I 1810-0384, 50 nsec delay, taps
at 10 nsec intervals)
where it is delayed 40 nsec
determines which halt of
the address is
fed through the
address multiplexers (see section 3.4.2).