Whether the multiplexer is in the refresh or memory state is controlled
by a 74LS74 D-flip flop
This flip flop can be set to the re-
fresh state in one of two ways:
the power on signal is fed to the pre-
set input to initialize the system and to allow for continuous refresh
during power on.
flop can also
clocked to the refresh
state by the signal RFSH (U14-8) which indicates the start of a refresh
The multiplexor is reset to the memory state by the signal RFSH
(U13-5) at the clear input.
This occurs halfway through the
time of the previous refresh cycle to allow the
dresses sufficient setup time before the next memory cycle.
generator consists of a
This counter is allowed to come up in an indeterminant
state and is then continuously clocked through the 128 possible refresh
The eigth bit also counts although it is not necessary as
refresh address line.
The counter is clocked by the signal COUNT (U26-
COUNT is the inverted refresh row address strobe,
clocked each refresh cycle by the
trailing edge of the row address strobe.
Each row of the dynamic memories must
Since each memory is organized into 128 rows,
cycles every 2 msec to avoid loss of information.
that a refresh cycle must occur every 15.63 usec.
The system clock is
If this clock is divided by 64 and the resulting edge used
to trigger a refresh cycle, a refresh will occur every 13.02 usec.