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HP 13255 Manual page 10

Memory controller module
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13255
Memory Controller
13255-91252/08
REV JUN-23-81
3.4.4
Whether the multiplexer is in the refresh or memory state is controlled
by a 74LS74 D-flip flop
(U24).
This flip flop can be set to the re-
fresh state in one of two ways:
the power on signal is fed to the pre-
set input to initialize the system and to allow for continuous refresh
during power on.
The flip
flop can also
be
clocked to the refresh
state by the signal RFSH (U14-8) which indicates the start of a refresh
cycle.
The multiplexor is reset to the memory state by the signal RFSH
STALL
(U13-5) at the clear input.
This occurs halfway through the
RAS
pre charge
time of the previous refresh cycle to allow the
memory ad-
dresses sufficient setup time before the next memory cycle.
3.5
REFRESH
ADDRESS
GENERATOR
3.6
3.6.1
The
refresh address
generator consists of a
74LS393 dual
four
bit
counter
(U45).
This counter is allowed to come up in an indeterminant
state and is then continuously clocked through the 128 possible refresh
addresses.
The eigth bit also counts although it is not necessary as
a
refresh address line.
The counter is clocked by the signal COUNT (U26-
6).
COUNT is the inverted refresh row address strobe,
and therefore
the
refresh
address
generator
is
clocked each refresh cycle by the
trailing edge of the row address strobe.
REFRESH TIMER
Each row of the dynamic memories must
be
completely refreshed
every 2
msec.
Since each memory is organized into 128 rows,
there must
be
128
refresh
cycles every 2 msec to avoid loss of information.
This means
that a refresh cycle must occur every 15.63 usec.
The system clock is
4.915 MHz.
If this clock is divided by 64 and the resulting edge used
to trigger a refresh cycle, a refresh will occur every 13.02 usec.

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