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HP 13255 Manual page 12

Memory controller module
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13255
Memory Controller
13255-91252/10
REV JUN-23-B1
3.B
3.B.1
3.B.2
3.B.3
BUS INTERFACE AND BOARD SELECT CIRCUITRY
The bus interface circuitry consists of several buffer drivers,
a wait
state generator and an
10
port designed to
be
used by OEM's for soft-
ware protection.
The bus signals SYSCLK,
REQ, and PON are buffered
by
74LS244 drivers to reduce loading.
In addition,
SYSCLK and REQ are
also inverted to
be
used in that state by the timing circuitry.
The Memory Controller Module requires one additional wait state
be
add-
ed to
the normal bus cycle in order to provide sufficient time to ac-
complish memory reads
and writes.
To
add this extra state,
a wait
state
latch is used.
This latch is a 74LSl12
J-K
flip flop
(U44).
This flip flop is set by
(071-9),
which signals the start of a memory
cycle and is
cleared by CAS,
the column address strobe.
This timing
results in the addition of one extra wait state.
WAIT is driven on to
the bus by a 74s03 open collector NAND gate (U42-3).
The
Memory Controller Module
incorporates a feature
which will allow
any
interested party to protect his applications software on the 2647F
by providing space for a four byte code which can
be
burned into a 32xB
PROM by the user;
this
code
can
be
used to encrypt the applications
software by any number of algorithms.
U41 is a socket for a 32xB field
programmable PROM
(Harris 7603 or equivalent).
The four byte code can
be accessed by reading
10
ports BAOO,
BA02, BA04,
and
BA06
(hex).
The
codes will appear to the processor to
be
the inverted state of what is
encoded in the PROM.

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