BUS INTERFACE AND BOARD SELECT CIRCUITRY
The bus interface circuitry consists of several buffer drivers,
state generator and an
port designed to
used by OEM's for soft-
The bus signals SYSCLK,
REQ, and PON are buffered
74LS244 drivers to reduce loading.
SYSCLK and REQ are
also inverted to
used in that state by the timing circuitry.
The Memory Controller Module requires one additional wait state
the normal bus cycle in order to provide sufficient time to ac-
complish memory reads
add this extra state,
latch is used.
This latch is a 74LSl12
This flip flop is set by
which signals the start of a memory
cycle and is
cleared by CAS,
the column address strobe.
results in the addition of one extra wait state.
WAIT is driven on to
the bus by a 74s03 open collector NAND gate (U42-3).
Memory Controller Module
incorporates a feature
which will allow
interested party to protect his applications software on the 2647F
by providing space for a four byte code which can
burned into a 32xB
PROM by the user;
used to encrypt the applications
software by any number of algorithms.
U41 is a socket for a 32xB field
(Harris 7603 or equivalent).
The four byte code can
be accessed by reading
codes will appear to the processor to
the inverted state of what is
encoded in the PROM.