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Mirror Mode
Use this feature to confi gure the mirror mode settings for all 1LM/2LM memory modules
installed in the system which will create a duplicate copy of data stored in the memory to
increase memory security, but it will reduce the memory capacity into half. The options are
Disable, Mirror Mode 1LM, and Mirror Mode 2LM.
Note: The setting for this feature can be edited when the item below: ADDDC Sparing
is set to Disable.
UEFI ARM Mirror
If this feature is set to Enable, mirror mode confi guration settings for UEFI-based Address
Range memory will be enabled upon system boot. This will create a duplicate copy of data
stored in the memory to increase memory security, but it will reduce the memory capacity
into half. The options are Disable and Enable.
Note: The setting for this feature can be edited when both ADDDC Sparing and Mirror
Mode are set to Disable.
Memory Rank Sparing
Select Enable to support memory-rank sparing to optimize memory performance. The
options are Enable and Disable.
Notes. 1: This feature can will not be available when the item: Memory Mirror Mode
is set to Enabled. 2: When this feature: Memory Rank Sparing is set to Enabled, the
following item will be available:
Multi Rank Sparing (Available when Memory Rank Sparing is set to Enable)
Use this feature to set the multiple rank sparing number. The default setting and the
maximum is two ranks per channel. The options are One Rank and Two Rank.
Correctable Error Threshold
Use this item to enter the threshold value for correctable memory errors. The default setting
is 100.
Intel Run Sure (Available when this feature is supported by the CPU)
Select Enable to support Intel® Run Sure Technology to further enhance critical data
protection and to increase system uptime and resiliency. The options are Enable and
Disable.
SDDC Plus One (Available when this feature is supported by the CPU & the item:
Intel Run Sure is set to Disable)
SDDC (Single Device Data Correction) checks and corrects single-bit or multiple-bit (4-bit
max.) memory faults that affect an entire single x4 DRAM device. SDDC Plus One is the
enhanced feature to SDDC. SDDC+1 will spare the faulty DRAM device out after an SDDC
event has occurred. After the event, the SDDC+1 ECC mode is enabled to protect against
any additional memory failure caused by a 'single-bit' error in the same memory rank. The
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Chapter 4: BIOS
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