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Super X11DPFF-SN User's Manual
Reset Trigger ADR (Available when an NVDIMM is detected & the item above: Enable
ADR is set to Enable)
Upon system power loss, an ADR (Automatic Diagnostic Repository) sequence will be
triggered to allow ADR to fl ush the write-protected data buffers in the memory controller and
place the DRAM in self-refresh. When this process is complete, the NVDIMM will then take
control of the DRAM and transfer the contents to the onboard Flash. After the transfer is
complete, the NVDIMM goes into a zero power state. The data transferred will be retained
for the duration specifi ed by the fl ash. The options are Enable and Disable.
S5 Trigger ADR (Available when an NVDIMM is detected & the item above: Enable
ADR is set to Enable)
Select Enabled to support S5-Triggered ADR to enhance system performance and data
integrity. The options are Disabled and Enabled.
2X Refresh
Select Enable for memory 2X refresh support to enhance memory performance. The options
are Enable and Auto.
Page Policy
Use this feature to set the page policy for onboard memory support. The options are Closed,
Adaptive, and Auto.
IMC Interleaving
Use this feature to confi gure interleaving settings for the IMC (Integrated Memory
Controller), which will improve memory performance. The options are 1-way Interleave,
2-way Interleave, and Auto.
Memory Topology
This item displays the information of onboard memory modules as detected by the
BIOS.
•
P1DIMMA1/P1DIMMB1/P1DIMMC1/P1DIMMD1/P1DIMME1/P1DIMMF1
•
P2DIMMA1/P2DIMMB1/P2DIMMC1/P2DIMMD1/P2DIMME1/P2DIMMF1
Memory RAS (Reliability_Availability_Serviceability) Confi guration
Use this submenu to confi gure the following Memory RAS settings.
Static Virtual Lockstep Mode
Select Enable to support the Static Virtual Lockstep mode to enhance memory performance.
The options are Enable and Disable.
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