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The AKD4953A-B is an evaluation board for the AK4953A 24bit CODEC with built-in PLL and MIC/HP/SPK
Amplifier. The AKD4953A-B has the interface with AKM's A/D evaluation boards. Therefore, it's easy to
evaluate the AK4953A. The AKD4953A-B also has the digital audio interface and can achieve the interface
with digital audio systems via opt-connector.
Ordering Guide
AKD4953A-B ---
• Compatible with 2 types of interface
- Direct interface with AKM's A/D converter evaluation boards
- DIT/DIR with optical input/output
• 10pin header for serial control interface
J1
Mini
Jack
J2
Mini
Jack
J3
Mini
Jack
*Circuit diagram and PCB layout are attached at the end of this manual.
<KM104800>
Evaluation board Rev.0 for AK4953A
GENERAL DESCRIPTION
Evaluation board for AK4953A
(Cable for connecting with printer port of IBM-AT compatible PC and control software
are packed with this. This control software does not operate on Windows NT.)
VDD
5V
1.8V
3.3V
REG
REG
DVDD SVDD
TVDD
LIN1
RIN1
LIN2
AK4953A
RIN2
LIN3
RIN3
SPN
SPP
SPK
J5
Jack
Figure 1. AKD4953A-B Block Diagram
FUNCTION
GND
0V
AVDD
HPL
HPR
HP
Jack
J4
- 1 -
[AKD4953A-B]
AKD4953A-B
PORT4
(up-I/F)
PORT3
(DSP)
PORT2
Opt In
AK4118A
PORT1
(DIT/DIR)
Opt Out
2010/10

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Summary of Contents for AKM AKD4953A-B

  • Page 1 Evaluation board Rev.0 for AK4953A GENERAL DESCRIPTION The AKD4953A-B is an evaluation board for the AK4953A 24bit CODEC with built-in PLL and MIC/HP/SPK Amplifier. The AKD4953A-B has the interface with AKM’s A/D evaluation boards. Therefore, it’s easy to evaluate the AK4953A. The AKD4953A-B also has the digital audio interface and can achieve the interface with digital audio systems via opt-connector.
  • Page 2 [AKD4953A-B] BOARD OUTLINE CHART ■ Outline Chart Figure 2. AKD4649-B Outline Chart ■ Comment (1) J1, J2, J3 (Mini Jacks) Analog signal input. (2) J4, J5 (Mini Jacks) Analog signal output. (3) +5V, GND (Power Supply Terminal) Connect power supply with these terminals.
  • Page 3 [AKD4953A-B] Evaluation Board Manual Operation sequence 1) Set up the power supply lines. Name Color Voltage Comments Attention +5.0V +5.0V Regulator Power line is needed for this jack. Black Ground Power line is needed for this jack. Table 1.Set up of power supply lines 2) Set up the evaluation mode, jumper pins.
  • Page 4 [AKD4953A-B] (1-4) All interface signals including master clock are fed externally. PORT3 (DSP) is used. Nothing should be connected to PORT2 (DIR). JP13 JP14 JP16 JP12 JP15 JP11 BICK BICK2 MCKO LRCK LRCK2 (2) Master mode (2-1) Evaluation of Loop-back using MCLK of AK4118A...
  • Page 5 [AKD4953A-B] DIP Switch Set Up [S1] (SW DIP-4): Mode setting of the AK4118A. Name ON (“H”) OFF (“L”) Default DIF2 AK4118A Audio Format Setting DIF1 See Table 3 DIF0 OCKS1 AK4118A Master Clock Setting : See Table 4 Table 2. Mode Setting of the AK4118A...
  • Page 6 [AKD4953A-B] Other jumper pins set up 1. [JP1](SVDD) : Select SVDD Voltage 1.8V : 1.8V Input. 3.3V : 3.3V Input. <Default> 5V : 5V Input. from “+5V” terminal. 2. [JP4](I2C) : Select I/F Mode. OPEN : 3-wire Serial Mode. SHORT : I2C Bus Mode. <Default>...
  • Page 7: Pin Header

    [AKD4953A-B] Serial Control The AK4953A can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT4 (up/-I/F) with PC by 10 wire flat cable packed with the AKD4953A-B. Connect SCL/CCLK SDA/CDTI AKD4953A-B 10 wire 10pin 10pin Header...
  • Page 8 [AKD4953A-B] (2) Output Circuits 1. HP Output Circuit 0.22u 0.22u AVSS Figure 5 . HP Output Circuit 2. SPEAKER Output Circuit Figure 6 . SPEAKER Output Circuit <KM104800> 2010/10 - 8 -...
  • Page 9 10pin header. When running this control soft on the Windows 2000/XP, the driver which is included in the CD must be installed. Refer to the “Driver Control Install Manual for AKM Device Control Software” for installing the driver. When running this control soft on the windows 95/98/ME, driver installing is not necessary. This control soft does not support the Windows NT.
  • Page 10: Operation Overview

    [All Write]: Executing write commands for all registers displayed. [All Read]: Executing read commands for all registers displayed. (AKD4953A-B does not support READ function) [Save]: Saving current register settings to a file. [Load]: Executing data write from a saved file.
  • Page 11 [AKD4953A-B] ■ Tab Functions 1. [Function]: Function control This tab is for function control. Each operation is executed by the function buttons on the left side of the screen. Figure 8.Window of [Function] <KM104800> 2010/10 - 11 -...
  • Page 12 [AKD4953A-B] 1-1. System Clock, Audio I/F Setting When [System Clock Audio I/F] button is clicked, the window as shown in Figure 9 opens. This window is for System Clock and Audio I / F Setting. Refer to the datasheet for register settings of the AK4953A.
  • Page 13: Alc Setting

    [AKD4953A-B] 1-2. ALC Setting When [ALC Setting] button is clicked, the window as shown in Figure 10 opens. This window is for ALC setting. Refer to the datasheet for register settings of the AK4953A. Figure 10. Window of [ALC Setting] <KM104800>...
  • Page 14: Volume Setting

    [AKD4953A-B] 1-3. Volume Setting When [Volume Setting] button is clicked, the window as shown in Figure 11 opens. This window is for Volume setting. Refer to the datasheet for register settings of the AK4953A. Register map Figure 11. Window of [Volume Setting] The volume can be controlled by slide bars.
  • Page 15: Beep Setting

    [AKD4953A-B] Volume Control by Pull-down Menu Slide bar is moved to the selected value Figure 12. Window of [Volume] The volume can also be changed by writing a value in a dialog box. The slide bar is moved to the value that written in the dialog box.
  • Page 16: Digital Filter Setting

    [AKD4953A-B] 1-5. Digital Filter Setting A calculation of a coefficient of Digital Programmable Filters such as HPF and EQ filters, a register writing and a frequency response checking of HPF and EQ filter can be made. When [Digital Filter] button is clicked, the window as shown in Figure 14 opens.
  • Page 17: Parameter Setting

    [AKD4953A-B] 1-5-1. parameter Setting (1) Please set a parameter of each Filter. Parameter Function Setting Range Sampling Rate Sampling frequency (fs) 7350Hz ≤ fs ≤ 48000Hz Cut Off Frequency High pass filter cut off frequency fs/10000 ≤ Cut Off Frequency≤ (0.497 * fs)
  • Page 18 [AKD4953A-B] 1-5-2. A calculation of a register A register set value is displayed when push a [Register Setting] button. When a value out of a setting range is set, error message is displayed, and a calculation of register setting is not carried out.
  • Page 19 [AKD4953A-B] 1-5-3. Indication of a frequency characteristic A frequency characteristic is displayed when push a [Frequency Response] button. Then, a register set point is also updated. Change "Frequency Range", and indication of a frequency characteristic is updated when push a [UpDate] button.
  • Page 20 [AKD4953A-B] Setting of center frequency: 4400Hz, 5000Hz, 5400Hz / Band Width: 200Hz(3 band common) Figure 18. When there is no center frequency revision Setting of center frequency: 4400Hz, 5000Hz, 5400Hz / Band Width : 200Hz(3 band common) Figure 19. When there is a center frequency revision <KM104800>...
  • Page 21: Reg]: Register Map

    Button Up indicates “L” or “0” and the bit name is in blue (when read only it is in gray) Grayout registers are Read Only registers. They can not be controlled. (AKD4953A-B does not support READ function) The registers which is not defined in the datasheet are indicated as “---”.
  • Page 22 [AKD4953A-B] [Write]: Data Writing Dialog It is for when changing two or more bits on the same address at the same time. Click [Write] button located on the right of the each corresponded address for a pop-up dialog box. When checking the checkbox, the register will be “H” or “1”, when not checking the register will be “L” or ”0”.
  • Page 23: Tool]: Testing Tools

    [AKD4953A-B] 3. [Tool]: Testing Tools This tab screen is for evaluation testing tool. Click buttons for each testing tool. Figure 22.Window of [Tool] <KM104800> 2010/10 - 23 -...
  • Page 24 [AKD4953A-B] ■ Dialog Boxes 1. [All Reg Write]: All Reg Write dialog box Click [All Reg Write] button in the main window to open register setting files. Register setting files saved by [SAVE] button can be applied. Figure 23. Window of [All Reg Write] [Open (left)]: Selecting a register setting file (*.akr).
  • Page 25 [Read]: Reading from the address specified by “Address” box. The result will be shown in the Read Data Box in hexadecimal numbers. (AKD4953A-B does not support READ function) [Close]: Closing the dialog box and finish the process. Data writing can be cancelled by this button instead of [Write] button.
  • Page 26: Sequence Setting

    [AKD4953A-B] 3. [Sequence]: Sequence Dialog Box Click [Sequence] button to open register sequence setting dialog box. Register sequence can be set in this dialog box. Figure 25. Window of [Sequence] Sequence Setting Set register sequence by following process bellow. (1) Select a command Use [Select] pull-down box to choose commands.
  • Page 27: Control Buttons

    [AKD4953A-B] (2) Input sequence [Address]: Data address [Data]: Writing data [Mask]: Mask [Data] box data is ANDed with [Mask] box data. This is the actual writing data. When Mask = 0x00, current setting is hold. When Mask = 0xFF, the 8bit data which is set in the [Data] box is written.
  • Page 28 [AKD4953A-B] 4. [Sequence(File)]: Sequence Setting File Dialog Box Click [Sequence(File)] button to open sequence setting file dialog box. Those files saved in the “Sequence setting dialog” can be applied in this dialog. Figure 26. Window of [Sequence(File)] [Open (left)] : Opening a sequence setting file (*.aks).
  • Page 29 [AKD4953A-B] MEASUREMENT RESULTS [Measurement condition] Measurement unit : Audio Precision, System two Cascade MCKI : 256fs (11.2896MHz,24.576MHz) BICK : 64fs : 44.1kHz,96kHz : 24bit Measurement Mode : EXT Slave Mode Power Supply : SVDD=AVDD=TVDD=3.3V, DVDD=1.8V Input Frequency : 1kHz Measurement Frequency : 20 ~ 20kHz...
  • Page 30 [AKD4953A-B] PLOT DATA ADC (LIN1/RIN1 ADC) (+0dB) fs=44.1kHz Figure 28. FFT Plot (Input level= -1dBFS) Figure 29. FFT Plot (Input level= -60dBFS) <KM104800> 2010/10 - 30 -...
  • Page 31 [AKD4953A-B] fs=44.1kHz Figure 30. FFT Plot (No signal) Figure 31. THD+N vs. Input Level (fin=1kHz) <KM104800> 2010/10 - 31 -...
  • Page 32 Figure 32. THD+N vs. Input Frequency (C24 and C25: Ceramic Capacitor ) In this case, a ceramic capacitor is used LIN1 and RIN1 pin on the AKD4953A-B.As the performance of a ceramic capacitor is not so good about low frequency signal. Refer to Figure 33 about the performance of AK4953A.
  • Page 33 [AKD4953A-B] fs=44.1kHz Figure 34. Linearity (fin=1kHz) Figure 35. Frequency Response (Input level=-1dBFS) <KM104800> 2010/10 - 33 -...
  • Page 34 [AKD4953A-B] fs=44.1kHz Figure 36. Crosstalk Plot (Input level=-1dBFS) <KM104800> 2010/10 - 34 -...
  • Page 35 [AKD4953A-B] ADC (LIN1/RIN1 ADC) (0dB) fs=96kHz Figure 37. FFT Plot (Input level= -1dBFS) Figure 38. FFT Plot (Input level= -60dBFS) <KM104800> 2010/10 - 35 -...
  • Page 36 [AKD4953A-B] fs=96kHz Figure 39. FFT Plot (No signal) Figure 40. THD+N vs. Input Level (fin=1kHz) <KM104800> 2010/10 - 36 -...
  • Page 37 Figure 41. THD+N vs. Input Frequency (C24 and C25: Ceramic Capacitor ) In this case, a ceramic capacitor is used LIN1 and RIN1 pin on the AKD4953A-B.As the performance of a ceramic capacitor is not so good about low frequency signal. Refer to Figure 42 about the performance of AK4953A.
  • Page 38 [AKD4953A-B] fs=96kHz Figure 43. Linearity (fin=1kHz) Figure 44. Frequency Response (Input level=-1dBFS) <KM104800> 2010/10 - 38 -...
  • Page 39 [AKD4953A-B] fs=96kHz Figure 45. Crosstalk Plot (Input level=-1dBFS) <KM104800> 2010/10 - 39 -...
  • Page 40 [AKD4953A-B] PLOT DATA ADC (LIN1/RIN1 ADC) (+20dB) fs=44.1kHz Figure 46. FFT Plot (Input level= -1dBFS) Figure 47. FFT Plot (Input level= -60dBFS) <KM104800> 2010/10 - 40 -...
  • Page 41 [AKD4953A-B] fs=44.1kHz Figure 48. FFT Plot (No signal) Figure 49. THD+N vs. Input Level (fin=1kHz) <KM104800> 2010/10 - 41 -...
  • Page 42 Figure 50. THD+N vs. Input Frequency (C24 and C25: Ceramic Capacitor ) In this case, a ceramic capacitor is used LIN1 and RIN1 pin on the AKD4953A-B.As the performance of a ceramic capacitor is not so good about low frequency signal. Refer to Figure 51 about the performance of AK4953A.
  • Page 43 [AKD4953A-B] fs=44.1kHz Figure 52. Linearity (fin=1kHz) Figure 53. Frequency Response (Input level=-1dBFS) <KM104800> 2010/10 - 43 -...
  • Page 44 [AKD4953A-B] fs=96kHz Figure 54. Crosstalk Plot (Input level=-1dBFS) <KM104800> 2010/10 - 44 -...
  • Page 45 [AKD4953A-B] ADC (LIN1/RIN1 ADC) (+20dB) fs=96kHz Figure 55. FFT Plot (Input level= -1dBFS) Figure 56. FFT Plot (Input level= -60dBFS) <KM104800> 2010/10 - 45 -...
  • Page 46 [AKD4953A-B] fs=96kHz Figure 57. FFT Plot (No signal) Figure 58. THD+N vs. Input Level (fin=1kHz) <KM104800> 2010/10 - 46 -...
  • Page 47 Figure 59. THD+N vs. Input Frequency (C24 and C25: Ceramic Capacitor ) In this case, a ceramic capacitor is used LIN1 and RIN1 pin on the AKD4953A-B.As the performance of a ceramic capacitor is not so good about low frequency signal. Refer to Figure 60 about the performance of AK4953A.
  • Page 48 [AKD4953A-B] fs=96kHz Figure 61. Linearity (fin=1kHz) Figure 62. Frequency Response (Input level=-1dBFS) <KM104800> 2010/10 - 48 -...
  • Page 49 [AKD4953A-B] fs=96kHz Figure 63. Crosstalk Plot (Input level=-1dBFS) <KM104800> 2010/10 - 49 -...
  • Page 50 [AKD4953A-B] DAC (DAC HPL/HPR) fs=44.1kHz Figure 64. FFT Plot (Input level= 0dBFS) Figure 65. FFT Plot (Input level= -3dBFS) <KM104800> 2010/10 - 50 -...
  • Page 51 [AKD4953A-B] fs=44.1kHz Figure 66. FFT Plot (No signal) Figure 67. THD+N vs. Input Level (fin=1kHz) <KM104800> 2010/10 - 51 -...
  • Page 52 [AKD4953A-B] fs=44.1kHz Figure 68. THD+N vs. Input Frequency (Input level=-3dBFS) Figure 69. Linearity (fin=1kHz) <KM104800> 2010/10 - 52 -...
  • Page 53 [AKD4953A-B] fs=44.1kHz Figure 70. Frequency Response (Input level=0dBFS) Figure 71. Crosstalk Plot (Test Point is device pin) <KM104800> 2010/10 - 53 -...
  • Page 54 [AKD4953A-B] DAC (DAC HPL/HPR) fs=96kHz Figure 72. FFT Plot (Input level= 0dBFS) Figure 73. FFT Plot (Input level= -3dBFS) <KM104800> 2010/10 - 54 -...
  • Page 55 [AKD4953A-B] fs=96kHz Figure 74. FFT Plot (No signal) Figure 75. THD+N vs. Input Level (fin=1kHz) <KM104800> 2010/10 - 55 -...
  • Page 56 [AKD4953A-B] fs=96kHz Figure 76. THD+N vs. Input Frequency (Input level=-3dBFS) Figure 77. Linearity (fin=1kHz) <KM104800> 2010/10 - 56 -...
  • Page 57 [AKD4953A-B] fs=96kHz Figure 78. Frequency Response (Input level=0dBFS) Figure 79. Crosstalk Plot (Test Point is device pin) <KM104800> 2010/10 - 57 -...
  • Page 58 [AKD4953A-B] DAC (DAC SPK, SPKG1-0="00") fs=44.1kHz Figure 80. FFT Plot (Input level= -0.5dBFS) Figure 81. FFT Plot (Input level= -60dBFS) <KM104800> 2010/10 - 58 -...
  • Page 59 [AKD4953A-B] fs=44.1kHz Figure 82. FFT Plot (No Signal) Figure 83. THD+N vs. Input Level (fin=1kHz) <KM104800> 2010/10 - 59 -...
  • Page 60 [AKD4953A-B] fs=44.1kHz Figure 84. THD+N vs. Input Frequency (Input level=-0.5dBFS) Figure 85. Linearity (fin=1kHz) <KM104800> 2010/10 - 60 -...
  • Page 61 [AKD4953A-B] fs=44.1kHz Figure 86. Frequency Response (Input level=-0.5dBFS) Figure 87. THD+N vs. Output Power <KM104800> 2010/10 - 61 -...
  • Page 62: Revision History

    AKM assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein.
  • Page 63 3-wire DMDAT CDTI/SDA DMCLK JP10 JP10 CCLK LIN1/RIN1 LIN1/RIN1 3-wire CSN/CAD0 AVSS Title Title Title - 63 - AKD4953A-B AKD4953A-B AKD4953A-B Size Size Size Document Number Document Number Document Number AK4953A AK4953A AK4953A Date: Date: Date: Monday, October 04, 2010...
  • Page 64 0.1u 0.1u uP-I/F uP-I/F CAD0 AVSS AVSS (short) (short) OPT-IN OPT-IN AVSS - 64 - Title Title Title AKD4953A-B AKD4953A-B AKD4953A-B Size Size Size Document Number Document Number Document Number DIR/DIT DIR/DIT DIR/DIT Date: Date: Date: Monday, October 04, 2010...

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