Related Manuals for ADLINK Technology PXI-2020
Summary of Contents for ADLINK Technology PXI-2020
- Page 1 PXI-2020/2022 8/16-CH 16-Bit 250 KS/s Simultaneous Sampling Card User’s Manual 2.01 Manual Rev. October 4, 2010 Revision Date: 50-17032-2010 Part No: Advance Technologies; Automate the World.
- Page 2 Copyright 2010 ADLINK TECHNOLOGY INC. All Rights Reserved. The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer.
- Page 3 Address: 5215 Hellyer Avenue, #110, San Jose, CA 95138, USA Tel: +1-408-360-0200 Toll Free: +1-800-966-5200 (USA only) Fax: +1-408-360-0222 Email: info@adlinktech.com ADLINK Technology (China) Co., Ltd. Address: (201203) 300 Fang Chun Rd., Zhangjiang Hi-Tech Park, Pudong New Area, Shanghai, 201203 China Tel: +86-21-5132-8988 Fax:...
- Page 4 Address: 84 Genting Lane #07-02A, Cityneon Design Centre, Singapore 349584 Tel: +65-6844-2261 Fax: +65-6844-2263 Email: singapore@adlinktech.com ADLINK Technology Singapore Pte. Ltd. (Indian Liaison Office) Address: No. 1357, "Anupama", Sri Aurobindo Marg, 9th Cross, JP Nagar Phase I, Bangalore - 560078, India Tel: +91-80-65605817 Fax: +91-80-22443548 Email:...
-
Page 5: Table Of Contents
Table of Contents Table of Contents..............i List of Tables................iii List of Figures ................ iv 1 Introduction ................ 1 Features................2 Applications ................. 3 Specifications............... 3 Performance ................ 8 2 Getting Started ..............9 Installation Environment ............9 Package Contents ............. 10 Mechanical Drawing and I/O Connectors ...... - Page 6 Timebase Exporting ............30 Trigger Sources ..............31 Software Trigger ............31 External Digital Trigger ..........31 PXI Star Trigger ............32 PXI Trigger Bus ............32 Trigger Signal Exporting ..........33 User-controllable Timing Signals ........34 DAQ timing signals ............35 Auxiliary Function Inputs (AFI) ........
-
Page 7: List Of Tables
Table 2-3: TRG IO, as an Output Port ........13 Table 2-4: CLK IN ..............13 Table 2-5: CLK OUT0/OUT1, as an Output Port ..... 13 Table 3-1: PXI-2020/2022 68-pin VHDCI-type Pin Assignment 17 Table 3-2: 68-pin VHDCI-type Connector Legend ....18 Table 4-1: Basic Counters ............25... - Page 8 Figure 3-2: Floating Source and Differential Input ..... 22 Figure 4-1: PXI-2022 Functional Block Diagram......23 Figure 4-2: PXI-2020/2022 Analog Input Path ......24 Figure 4-3: Basic Acquisition Timing of PXI-2020/2022..... 26 Figure 4-4: PXI-2022 Timebase Source and Architecture..28 Figure 4-5: Configuring Different Sampling Rate of PXI-2022.
-
Page 9: Introduction
PXI Star trigger controller slot. The precision 10 MHz clock that comes from the PXI backplane can also be used as one of the timebase sources. Combining these PXI trigger fea- tures with the interface of the PXI-2020/2022 makes it very easy to synchronize multiple modules. Introduction... -
Page 10: Features
Calibration The PXI-2020/2022 includes a precision on-board reference with very low temperature drift. This feature not only provides a stable calibration source for auto-calibration but also maintains stable acquisition accuracy over a wide temperature range. The auto- mated calibration process can be done through software without need for any manually adjustments. -
Page 11: Applications
Laboratory Automation Biotech measurement 1.3 Specifications Basic Specifications Analog Input[1] Model Number PXI-2020 PXI-2022 Number of channels: (pro-grammable) 8 differential 16 differential A/D converter : AD7685 or equivalent Maximum sampling rate: 250 kS/s (each channel) Resolution:... -
Page 12: Table 1-2: Triggers
Triggers Trigger Specifications Model Name PXI-2020/2022 (1)Software (2)AFI [0..7] (3)PXI Star Trigger Trigger Sources (4)PXI Trigger Bus[5] (SSI) (refer to section 4.4 for details) (5)SMB Trigger I/O (please refer to chapter 2.3 for details) *GA 3-8 can use (1), (2), (4), (5) as output signals. -
Page 13: Table 1-3: Digital I/O
Digital I/O Digital I/O Specifications Model Name PXI-2020/2022 Number of Channel 4 input/output Input 3.3 V or 5 V TTL Compatibility Output 3.3 V TTL Input low voltage: 0.8 V (max) Input Logic Levels Input high voltage: 2.0 V(min) Output low voltage: 0.4 V (max) Output Logic Levels Output high voltage: 2.8 V (min) -
Page 14: Table 1-5: Timebase System
Timebase System Timebase Specifications Model Name PXI-2020/2022 (1) Internal: onboard 80MHz oscillator Timebase Source (2) External from hardware IO Timebase divided by 32-bit counter. TIMEBASE(80MHz) divider to the achieve equivalent sampling rate of DAQ. The equa- tion is: Sampling rate = TIMEBASE / ScanIntrv... -
Page 15: Table 1-7: General
General General Specifications Model Name PXI-2020/2022 Single 3U PXI module, 100mm by 160mm Dimensions (not including connector) Connector 68-pin VHDCI-type female Ambient temperature: 0 to 55°C Operating Environment Relative humidity: 10% to 90% non-con- densing Ambient temperature: -20 to 80°C... -
Page 16: Performance
1.4 Performance Analog Input Measurement[1] Model Number PXI-2020/2022 Function Result under 25°C ± 5°C Offset Error (gain = 1) ±0.6 mV (Typical) Gain Error (gain = 1) ±0.02% (Typical) gain = 1 : 1 MHz –3dB small signal bandwidth gain = 4 : 700 KHz gain = 1 : 0.5 mVrms... -
Page 17: Getting Started
This chapter describes the proper installation environment, instal- lation procedures, its package contents and basic information user should be aware of. The PXI-2020/2022 performs an automatic configuration of the IRQ, and port address. The PCI_SCAN soft- ware utility can be used to read the system configuration. -
Page 18: Package Contents
2.2 Package Contents Before continuing, check the package contents for any damage and check if the following items are included in the packaging: PXI-2020/2022 Simultaneous Data Acquisition Card ADLINK All-in-one DVD Software Installation Guide PXI-2020/2022 User’s Manual. -
Page 19: Mechanical Drawing And I/O Connectors
2.3 Mechanical Drawing and I/O Connectors Figure 2-1: PXI-2020/2022 PCB Layout The ADLINK PXI-2020/2022 is packaged in a Euro-card form fac- tor compliant with PXI specifications measuring 160 mm in length and 100 mm in height (not including connectors). The connector types and functions are described as follows. -
Page 20: Table 2-1: Smb Connector
SMB Connector SMB Connector 1: TRG IO SMB Connector 2: Sync CLK_OUT1 SMB Connector 3: Sync CLK_OUT0 SMB Connector 4: CLK IN Connector Direction Type Description/Function Input The TRG IO is a bidirectional port for external digi- TRG IO Output tal trigger input or output. -
Page 21: Table 2-3: Trg Io, As An Output Port
TRG IO, as an Output Port Connector type Compatibility 3.3 V TTL Output low voltage: 0.2 V (max) Output Logic Level Output high voltage: 2.4 V (min) Driving Capability 8 mA Minimum Output Pulse Width 12.5 ns Table 2-3: TRG IO, as an Output Port CLK IN (External Clock from Front Panel) Connector Type Clock Type... -
Page 22: Installing The Module
2.4 Installing the module To install the PXI-2020/2022 module: 1. Turn off the PXI system/chassis and disconnect the power plug from the power source. 2. Align the module’s edge with the card guide in the PXI chassis. 3. Slide the module into the chassis, until resistance is felt from the PXI connector. -
Page 23: Software Support
2.5 Software Support ADLINK provides comprehensive software drivers and packages to suit various user approaches to building a system. Aside from programming libraries, such as DLLs, for most Windows-based systems, ADLINK also provides drivers for other application envi- ronment such as LabVIEW® and MATLAB®. ADLINK also pro- vides ActiveX component ware for measurement and SCADA/ HMI, and breakthrough proprietary software applications. -
Page 24: Pci Configuration
2.6 PCI Configuration 1. Plug and Play: As a plug and play component, the card requests an interrupt number via its PCI controller. The system BIOS responds with an interrupt assignment based on the card information and on known system parameters. These system parameters are determined by the installed driv- ers and the hardware load seen by the system. -
Page 25: Signal Connections
Signal Connections This chapter describes the connectors of the PXI-2020/2022, and the signal connection between the PXI-2020/2022 and external devices. 3.1 Connectors Pin Assignment The PXI-2020/2022 is equipped with one 68-pin VHDCI-type con- nector (ACL-10568-1). It is used for digital input/output, analog input, and ti-mer/counter signals, etc. -
Page 26: Table 3-2: 68-Pin Vhdci-Type Connector Legend
AIL14 AIH14 AGND AGND AIL7 AIH7 AIL15 AIH15 AGND AGND Table 3-1: PXI-2020/2022 68-pin VHDCI-type Pin Assignment Legend: Pin # Signal Name Reference Direction Description 58, 55, 52, 49, 46, 43, 40,37, Differential positive input AIH <0..15> AIL <0..15> Input 57, 54, 51, 48, for AI channel <0..15>... - Page 27 In-put/Output Programmable DIO pins 25, 26, 59, 60 DGND -------- -------- Table 3-2: 68-pin VHDCI-type Connector Legend Note: Pins 2, 5, 8, 11, 14, 17, 20, 23, 36, 39, 42, 45, 48, 51, 54, and 57 are NC for the PXI-2020. Signal Connections...
-
Page 28: Analog Input Signal Connection
A ground-referenced signal means it is connected in some way to the building system. That is, the signal source is already con- nected to a common ground point with respect to the PXI-2020/ 2022, assuming that the computer is plugged into the same power system. -
Page 29: Input Connect Configurations - Differential Input Mode
Figure 3-2 shows how to connect a floating signal source to the PXI-2020/2022 card in differential input mode. For floating signal sources, you need to add a resistor at each channel to provide a bias return path. -
Page 30: Figure 3-2: Floating Source And Differential Input
Input Multipexer Instrumentation x = 0, ..., 31 Amplifier AIxH Ground Referenced To A/D Signal Converter Source AIxL AIGND Figure 3-2: Floating Source and Differential Input Signal Connections... -
Page 31: Function Block And Operation Theory
Function Block and Operation Theory The operation theory of the functions on the PXI-2020/2022 is described in this chapter. The functions include the A/D conver- sion, Digital I/O and General Purpose Counter/Timer. The opera- tion theory can help you understand how to configure and program the PXI-2020/2022. -
Page 32: Basic Ai Acquisition
4.2.1 Analog Input Path The following figure shows the block diagram of the single analog input path of a PXI-2020/2022. Each path provides a choice of 1G Ω input impedance or high impedance. The gain amplifier is opti- mized for ±10 V and ±2.5 V input range with low noise and high dynamic range. -
Page 33: Table 4-1: Basic Counters
ter. Please refer to Table 4-1 below and Section “4.3.4” on page 30 for more details. Counter Name Length Valid value Description Scan Interval Counter. This counter is a TIMEBASE(80MHz) divider to the achieve equivalent sam-pling rate of DAQ. The equation is: Sampling rate = TIMEBASE / ScanIntrv ScanIntrv 32-bit... -
Page 34: Ai Data Format
Timing, trigger modes, trigger sources, and transfer me-thods are included in this section. The following table illustrates the idea transfer characteristics of various input ranges of the PXI-2020/2022. The data format of the PXI-2020/2022 is straight binary. Function Block and Operation Theory... -
Page 35: Table 4-2: Bipolar Analog Input Range And Output Digital Code
Description Bipolar Analog Input Range Digital code Full-scale Range ±10 V ±2.5 V Least significant bit 305.2 uV 76.3 uV FSR-1LSB 9.999695 V 2.499924 V 7FFF Midscale +1LSB 305.2uV 76.3 uV 0001 Midscale 0000 Midscale –1LSB -305.2 uV -76.3 uV FFFF -FSR -10 V... -
Page 36: Adc Sampling Rate And Timebase Control
ADC15 Figure 4-4: PXI-2022 Timebase Source and Architecture. 4.3.1 Internal Oscillator The PXI-2020/2022 equips a high stability, low jitter oscillator for the ADCs. The oscillators are 80 MHz for the PXI-2020/2022. 4.3.2 External Clock through Front Panel When you need a specific timebase in some applications that the onboard oscillator is not achievable, a clock from an external device can replace onboard oscillator. -
Page 37: External Clock From Pxi Interfaces
PXI_STAR as timebase clock source. Note that the function is only available when the PXI-2020/2022 is in a PXI system. It’s not sup- ported when the PXI-2020/2022 is in a CompactPCI system. Function Block and Operation Theory... -
Page 38: Sampling Rate Control
Figure 4-5: Configuring Different Sampling Rate of PXI-2022. 4.3.5 Timebase Exporting The PXI-2020/2022 can export timebase to one of the PXI trigger bus line 0. By software programming, you can pick up a trigger line to transmit timebase clock. This feature is very useful when syn- chronize to multiple measurement modules. -
Page 39: Trigger Sources
4.4 Trigger Sources In addition to the internal software trigger, the PXI-2020/2022 sup- ports external digital triggers from the front panel connector AFI[0…7], SMB TRIG I/O, PXI_STAR triggers, PXI Trigger Bus Line 5. You can configure the trigger source by software com- mand. -
Page 40: Pxi Star Trigger
The minimum pulse width requirement of this digi- tal trigger signal is 12.5 ns. 4.4.4 PXI Trigger Bus The PXI-2020/2022 utilizes PXI Trigger Bus[5] as System Syn- chronization In-terface (SSI). Using the interconnected bus pro- vided by PXI Trigger Bus, you can easily synchronize multiple modules. -
Page 41: Trigger Signal Exporting
4.4.5 Trigger Signal Exporting The PXI-2020/2022 can export trigger signals to following connec- tors/bus: SMB TRG IO on front panel, AFI0 on front panel and PXI Trigger Bus Line 5. The TRG IO on the front panel can also be... -
Page 42: User-Controllable Timing Signals
The entire DAQ timing of the PXI-2020/2022 series is composed of a bunch of counters and trigger signals in the FPGA. These tim- ing signals are related to the A/D conversions and Timer/Counter applications. -
Page 43: Daq Timing Signals
Timing Signal Category Corresponding Functionality SSI/PXI signals Multiple cards synchronization AFI signals Control PXI-2020/2022 by external timing signals SMB CLK IN Control PXI-2020/2022 by external timing signals AI_Trig_Out Control external circuitry or boards Table 4-3: Summary of User-controllable Timing Signals and Corresponding Functionalities 4.5.1 DAQ timing signals... -
Page 44: Auxiliary Function Inputs (Afi)
4.5.2 Auxiliary Function Inputs (AFI) You could use the AFI in applications that take advantage of exter- nal circuitry to directly control the PXI-2020/2022 series cards. The AFI includes 2 categories of timing signals: one group is the dedi- cated input, and the other is the multi-function input. -
Page 45: Trigger Modes
4.6 Trigger Modes There are four trigger modes working with trigger sources to initi- ate different data acquisition timing when a trigger event occurs. They are described in this section. 4.6.1 Post-trigger Acquisition Use post-trigger acquisition when you want to collect data after the trigger event, as illustrated in Figure 4-10. -
Page 46: Middle-Trigger Acquisition
The trigger event occurs after the specified amount of data has been acquired. However, if the trigger event occurs before the specified amount of data has been acquired, the acquisition engine will ignore the trigger signal until the specified amount of data has been acquired. -
Page 47: Delay-Trigger Acquisition
4.6.4 Delay-trigger Acquisition Use delay-trigger acquisition to delay the data collection after the trigger event, as illustrated in Figure 4-14. The delay time is speci- fied by a 32-bit counter value so that the maximum delay time is the period of TIMEBASE X (232 - 1), while the minimum delay is the period of timebase. -
Page 48: Synchronizing Multiple Modules
The bi-directional SSI I/Os provide a flexible connection between modules, which allows one SSI master PXI-2020/2022 to output the SSI signals to other slaves modules to receive the signals. Table 4-4 lists the summary of SSI timing signals and the functionalities. Figure 4-15 shows the architecture of SSI. -
Page 49: Ssi_Timebase
As an output, the SSI_TIMEBASE signal outputs the onboard LVTTL time-base through PXI trigger bus line 0. As an input, the PXI-2020/2022 accepts the SSI_TIMEBASE signal to be the source of timebase. In PXI form factor, we utilize the PXI trigger bus built on the PXI backplane to provide the necessary timing signal connections. - Page 50 For example: We want to synchronize the A/D operation through the SSI_ADCONV signal for 4 PXI-2020/2022 cards. Card 1 is the master, and Card 2, 3, 4 are slaves. Card 1 receives an external digital trigger to start the post trigger mode acquisi- tion.
-
Page 51: General Purpose Timer/Counter Operation
The output of timer/counter is GPTC_OUT. After power-up, GPTC_OUT is pulled high by a pulled-up resister about 10K ohms. Then GPTC_OUT goes low after the PXI-2020/2022 is ini- tialized. All the polarities of input/output signals can be programmed by software. -
Page 52: General Purpose Timer/Counter Modes
4.8.2 General Purpose Timer/Counter Modes Eight programmable timer/counter modes are provided. All modes start operating following a software-start signal that is set by the software. The GPTC software reset initializes the status of the counter and re-loads the initial value to the counter. The operation remains halted until the soft-ware-start is re-executed. -
Page 53: Figure 4-17: Mode 2 Operation
Mode 2: Single Period Measurement In this mode, the counter counts the period of the signal on GPTC_GATE in terms of GPTC_CLK. Initial count can be loaded from software. After the software-start, the counter counts the number of active edges on GPTC_CLK between two active edges of GPTC_GATE. -
Page 54: Figure 4-19: Mode 4 Operation
Mode 4: Single Gated Pulse Generation This mode generates a single pulse with programmable delay and pro-grammable pulse-width following the software-start. The two programmable parameters could be specified in terms of periods of the GPTC_CLK input by software. GPTC_GATE is used to enable/disable counting. When GPTC_GATE is inac- tive, the counter halts the current count value. -
Page 55: Figure 4-21: Mode 6 Operation
Mode 6: Re-triggered Single Pulse Generation This mode is similar to mode5 except that the counter gener- ates a pulse following every active edge of GPTC_GATE. After the software-start, every active GPTC_GATE edge triggers a single pulse with programmable delay and pulse-width. Any GPTC_GATE triggers that occur when the prior pulse is not completed would be ignored. -
Page 56: Figure 4-23: Mode 8 Operation
Mode 8: Continuous Gated Pulse Generation This mode generates periodic pulses with programmable pulse interval pulse-width following software-start. GPTC_GATE is used to enable/disable counting. When GPTC_GATE is inactive, the counter halts the current count value. Figure 4-23 illustrates the generation of two pulses with a pulse delay of four and a pulse-width of three. -
Page 57: Calibration
This chapter introduces the calibration process to minimize AD measurement errors and DA output errors. 5.1 Loading Calibration Constants The PXI-2020/2022 is factory calibrated before shipment by writ- ing the associated calibration constants of TrimDACs to the on- board EEPROM. TrimDACs are devices containing multiple DACs within a single package. -
Page 58: Auto-Calibration
5.2 Auto-calibration By using the auto-calibration feature of the PXI-2020/2022, the calibration software can measure and correct almost all the cali- bration errors without any external signal connections, reference voltages, or measurement devices. The PXI-2020/2022 has an on-board calibration reference to ensure the accuracy of auto-calibration. -
Page 59: Important Safety Instructions
Important Safety Instructions Please read and follow all instructions marked on the product and in the documentation before operating the system. Retain all safety and operating instructions for future use. Please read these safety instructions carefully. Please keep this User’s Manual for future reference. ... - Page 60 Openings in the case are provided for ventilation. Do not block or cover these openings. Make sure there is adequate space around the system for ventilation when setting up the work area. Never insert objects of any kind into the ventila- tion openings.
Need help?
Do you have a question about the PXI-2020 and is the answer not in the manual?
Questions and answers