Aaeon IMBA-Q77 User Manual page 81

I n d u s t r i a l M o t h e r b o a r d
CR F7h. (WDTO# Control & Status Register; Default 00h)
BIT READ/WRITE
7 R/W
6 R/W
5 Write "1" Only
R/W
4
Write"0"Clear
3~0 R/W
01h: Time-out occurs after 1 second/minute
02h: Time-out occurs after 2 second/minutes
03h: Time-out occurs after 3 second/minutes
...........................................................
FFh: Time-out occurs after 255 second/minutes
Mouse interrupt reset watch-dog timer enable
0: Watchdog timer is not affected by mouse interrupt.
1: Watchdog timer is reset by mouse interrupt.
Keyboard interrupt reset watch-dog timer enable
0: Watchdog timer is not affected by keyboard interrupt.
1: Watchdog timer is reset by keyboardd interrupt.
Trigger WDTO# event. This bit is self-clearing.
WDTO# status bit
0: Watchdog timer is running.
1: Watchdog timer issue time-out event.
These bits select IRQ resource for WDTO#. (02h for
SMI# event.)
Appendix A Programming the Watchdog Timer
I M B A - Q 7 7
DESCRIPTION
A-5