Table of Contents
Advertisement
PLL/Modulation Options Screen
Figure 3−3. PLL/Modulation Options Screen
The PLL/Modulations Options screen is divided into the following four
sections:
-
-
-
-
Press the Send Bits button located on the PLL/Modulation Options screen to
program the TRF4900. Press the Close button to return to the chip layout
screen.
3-8
APLL
Controls the acceleration factor for the PLL. The values are 0, 20, 40, 60,
80, 100, 120, and 140. Any changes are automatically updated in the PLL
and MM Options section of the main program screen after pressing the
Send Bits button located on the PLL screen.
NPLL
Controls the N-Divider of the PLL. The NPLL can be set to either 256 or
512. Any changes are automatically updated in the NPLL box on the main
program screen after pressing the Send Bits button located on the PLL
screen.
Modulation Mode
Allows the user to select FSK modulation. Any changes are automatically
updated in the MM box on the main program screen after pressing the
Send Bits button located on the PLL screen.
FSK Frequency Register
This section acts as a calculator and sets bits 20−13 of Word D to the user
defined bits. The bits of the FSK deviation register (DV7−DV0) can be set
individually by double clicking inside each DVx box. After setting all bits,
press the Send Bits button located on the PLL/Modulation Options screen.
The bits of the frequency register will be mapped to Word D on the main
program screen, and highlighted in green. Furthermore, Fout: TX_Data
High (MHz), Fout: TX_Data Low (MHz) frequencies, and their difference
(Delta Fout kHz), are calculated and displayed.
DV6 Display
Set to 1 by
Double Clicking
f
Frequency
1
915 MHz
f
Frequency
2
915.10 MHz
FSK Deviation
of 100 kHz
Send Bits
Button
Advertisement
Table of Contents
