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Circuit Description
5-2-2. Jupiter-2 Chip
KS32C6500 internal logic generates chip select
signals for both memory chips and peripherals. To
support external access, from one to three wait
cycles can be inserted under program control during
external accesses. A chip select signal line goes
active (low) whenever its corresponding device is
accessed over the external interface. The peripheral
addresses are located in data memory.
/SRAMCS : SRAM chip select active (low)
/ ROMCS : EP-ROM chip select active (low)
D0ÐD15 : 16 bit data bus
A0ÐA17 : address bus
OPERATING
PANEL
SERIAL
COMMUNICATION
HEAD
DRIVER
MOTOR
DRIVER
(CR, LF
MOTOR)
5-2
SDIP4
A0~A5
D0~D15
D0~D7
TXD
RXD
KS32C6500
PHINA~D
CONTROL
+24
Figure 5-2 Hardware Interface Signals
5-2-3. System Clock
The 30 MHz internal system clock frequency is
supplied by an external clock generator.
TAD PART
CONTROL
ONLY SF3000T
XIN
XOUT
/DMS
/RD/WR
D0~D7
A0~A14
/RASO~
/UCAS
/LCAS
/RD
D0~D15
A0~A17
/A16
/PMS
/RD/WR
D0~D7
A0~A4
/RESET
/RESTO
RTC
CRYSTAL
(32, 768KHZ)
DATA
MEMORY
(SRAM)
DRAM.
(USER MEMORY)
PROGRAM
MEMORY
(EPROM)
MODEM
GENERAL
PURPOSE I/ 0
Samsung Electronics
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