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Samsung SF-335T Repair Manual

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Repair Manual
SAMSUNG FACSIMILE
SF-330/331P/335T
C•O•N•T•E•N•T•S
1. Block Diagram
2. Connection Diagram
3. Circuit Description
4. Schematic Diagrams

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Summary of Contents for Samsung SF-335T

  • Page 1 Repair Manual SAMSUNG FACSIMILE SF-330/331P/335T C•O•N•T•E•N•T•S 1. Block Diagram 2. Connection Diagram 3. Circuit Description 4. Schematic Diagrams...
  • Page 3 This manual is made and described centering around circuit diagram and circuit description needed in the repair center in the form of appendix. Samsung Electronics Digital Printing CS Group Copyright (c) 2002. 07...
  • Page 4 OPE PCB : 247 x 95.5m m 30Pin 60 pin MAIN SIXSHOOTOR MODEM SMPS 4pin (14.4k) (+24V,-5V) MOTOR 2pin FM214 : SF-330/331P (3Pin Connector) CHORUS2 FM214-VS : SF-335T (DC) 2pin SPEAKER ERTE (Including IP) SF-331P ONLY SCAN MOTOR 5pin MOTOR (STEP) QUA RTER- (STEP) SDRAM FLASH...

  • Page 5: Connection Diagram

    R 29 (16X1) CIS_SI D_DET R 37 MIC_SIG ¡£ CIS_SIG R 39 AGND MIC_IN R 35 R 41 D_SCAN Only SF-335T DGND R 43 MODEM_TX R 45 AGND R 47 MODEM_RX TSR1 AGND +19.2V (R49) CIS_SIG HS_TX_CTL C 3 COL...

  • Page 6: Circuit Description

    CIRCUIT DESCRIPTION 3. Circuit Description 3.1 Main B’D 3.1.1 GENERAL DESCRIPTION Main circuit consists of mainly consists of CPU and the controller part with various types of built-in I/O device driver(built-in RISC Processor Core : ARM7TDMI), system memory part, Image control part (CHORUS-2) controlling input of image received from media and conversion.

  • Page 7: System Clock

    CIRCUIT DESCRIPTION 3.1.3.1 BLOCK DIAGRAM and MAIN CONTROLLER description <1> General description 3.1.3.2 S3C46Q0X FUNCTION DESCRIPTION MAIN CONTROLLER(S3C46Q0X,U12) consists of this <1> SYSTEM CLOCK system consists of CPU(ARM7TDMI RISC PROCES- SOR), 8K BYTES CACHE, DATA and ADDRESS BUS, There are two ways of Clock input method. One is the PLL deriding input frequency and CLOCK CONTROL part, method to make Master Clock(MCLK) at the internal PLL SERIAL COMMUNICATION part supporting UART, PRINT...
  • Page 8 CIRCUIT DESCRIPTION SHOOTER _SS_SW (U5) (0:15) (U7) (U4) _scs0 MOTOR MOTOR MOTOR (0:15) (SF-330 : U9) (SF-331P : U9) SF-330 : (0:11) (SF-335T : U8) (U12) SF331P: (0:11) SF-335T : (0:12) TX_A TX_nA TX_B (U2) MOTOR TX_nB CIS_LED CIS_CLK 3.3V (U10)
  • Page 9 CIRCUIT DESCRIPTION EXTCLK tRAD tRAD ADDR tRCD tRCD nGCSx Tacs Tcah tRWD tRWD Tocs Tacc Toch nGCSx ’1’ nBEx tRDD DATA tRDH <Figure 3. Flash Memory Read Timing> EXTCLK tRAD tRAD ADDR tRCD tRCD nGCSx Tacs Tcah tRWD tRWD Tocs Tacc Toch nGCSx...
  • Page 10 CIRCUIT DESCRIPTION SCLK SCKE ’1’ tSAD ADDR/BA tSAD AP/A10 tSCSD nGCSx tSRD nSRAS Trcd tSCD nSCAS tSBED nBEx tSWD tSDS DATA tSDH <Figure 5. SDRAM Read Timing>...
  • Page 11 CIRCUIT DESCRIPTION SCLK SCKE ’1’ tSAD ADDR/BA tSAD AP/A10 tSCSD nGCSx tSRD nSRAS Trcd tSCD nSCAS tSBED nBEx tSWD tSDD DATA tSDD <Figure 6. SDRAM Write Timing>...
  • Page 12 CIRCUIT DESCRIPTION SCLK SCKE ’1’ tSAD tSAD ADDR/BA tSAD AP/A10 tSCSD tSCSD nGCSx tSRD tSRD nSRAS tSCD nSCAS nBEx ’1’ tSWD DATA ’HZ’ <Figure 7. SDRAM Write Timing>...
  • Page 13 CIRCUIT DESCRIPTION SCLK SCKE ’1’ tSAD tSAD ADDR/BA tSAD AP/A10 tSCSD tSCSD nGCSx tSRD tSRD nSRAS tSCD nSCAS nBEx ’1’ tSWD DATA ’HZ’ <Figure 8. SDRAM auto Refresh Timing>...
  • Page 14 CIRCUIT DESCRIPTION SCLK tCKED tCKED SCKE tSAD tSAD ADDR/BA tSAD AP/A10 tSCSD tSCSD nGCSx ’1’ tSRD tSRD nSRAS ’1’ ’1’ tSCD ’1’ nSCAS ’1’ nBEx ’1’ tSWD ’1’ DATA ’HZ’ ’HZ’ <Figure 9. SDRAM Self Refresh Timing>...
  • Page 15 CIRCUIT DESCRIPTION <3> EXTERNAL DMA part <6> PARALLEL PORT INTERFACE division This system does not use External DMA part. This system does not use Parallel Port Interface Division. <4> DRAM control part <7> USB INTERFACE PART Since S3C46Q0X has the DRAM CONTROLLER build-in, 1.
  • Page 16 CIRCUIT DESCRIPTION 2. operation description This system, when Host and USB cables are connected, and when +5V is detected in power detector inside chip and Vbus, 3.3V comes out through Pull-uP terminal. This is also connected to DP in pattern of hardware and supports Full-speed. Utilizing Configuration Endpoint, EPO, in USB controller, Plug &...
  • Page 17 CIRCUIT DESCRIPTION 2. HEAD DATA OUTPUT FORMAT The 1 slice data [47:0] from the HDMA is outputted with the PHADR in order as below. <9> SYNCHRONOUS SERIAL INTERFACE PART It interfaces with Quarter-horse ASIC and consists of SMIC, SMID, PWM, and _RST. The Quarter-horse is the Motor Driver IC.
  • Page 18 CIRCUIT DESCRIPTION While transferring the motor phase, if there is NAK, the data transfer is automatically stopped and being in the IDLE condition. In the case, The S/W makes new value to transfer the data, or if the NAK Enable of the Control Register is set, automatically the same value is transferred for data transfer after for a while.Quarter-horse con- trols two Stepper motors (Line Feeder and Service Station) and one DC Motor (Carriage Motor).
  • Page 19 CIRCUIT DESCRIPTION 2. Chorus-2 Assigned GPO Ports for RHINE...
  • Page 20 CIRCUIT DESCRIPTION 3. Chorus-2 Assigned GPI Ports for RHINE 4. Chorus-2 Assigned GPIO Ports for RHINE...
  • Page 21 CIRCUIT DESCRIPTION 5. HP IMPORTANT ASIC Ports for RHINE...
  • Page 22 CIRCUIT DESCRIPTION 3.1.3.3 RESET circuit This system is configured with PRIMARY RESET(_RST) of Power Reset, Reset by WATCH DOG TIMER, external PRIMARY RESET, and SECOND RESET(__F_POR) which was done AND. PRIMARY RESET SYSTEM is used for resetting MAIN CON- TROLLER(U12) when System Power is authorized, and SECOND RESET resets FLASH MEMORY(U7). Figure below is BLOCK DIAGRAM related to the reset of entire system.

  • Page 23: Memory Configuration

    MEMORY applied in this system are FLASH MEMORY(U7) By each CHIP SELECT ( ROM_CS, _SCS0, _SD_RAS of 1Mbyte, SDRAM (SF-330/331P:U9 ; 2Mbyte ,/ SF-335T ,_SD_CAS ), FLASH MEMORY and SDRAM are selected, : U8 ; 8Mbyte) and DATA is accessed by HALF WORD unit.

  • Page 24: Block Diagram

    CIRCUIT DESCRIPTION 3.1.5.3 Block Diagram <Figure 16. Block Diagram of IP_TOP>...

  • Page 25: General Information

    CIRCUIT DESCRIPTION 3.1.6 QUARTERHORSE ASIC 3.1.6.1 General Information The Quarter-horse ASIC consists of the Serial Interface port which interfaces with the main controller, Linear Pre-regulator Circuit, Power On Reset Generation Circuit, and Motor Drive part. <1> SERIAL INTERFACE It interfaces with the Main Controller (S3C46Q0X), and consists of SMIC, SMID, PWM, and _RST. Please, refer to the picture 17 for the timing.
  • Page 26 CIRCUIT DESCRIPTION <2> SERIAL INTERFACE PIN NAME DESCRIPTION DIRECTION / TYPE preg Pre-regulator control analog/output DC motor driver and 5V regulator input supply voltage power/input DCMA DC motor drive half bridge A power/bidirectional DCMB DC motor drive half bridge B power/bidirectional DCPWM PWM input signal...
  • Page 27 CIRCUIT DESCRIPTION 3.1.6.2 QUARTERHORSE FUNCTION <1> PEN / MOTOR SUPPLY VOLTAGE REGULATOR It receives the inputted power of +24V, and the power flows to the buck type regulator, which consists of the external N-chan- nel FET and SCHOTTKY diode, to make +19.2V. The power uses as the main power of the ink head, CR, and LF, SS MOTOR. <2>...
  • Page 28 CIRCUIT DESCRIPTION 2. STEPPER MOTOR TRUTH TABLES <PAPER MOTOR> Inputs Outputs Whinny Register Bits Pin 38 (37) Pin 35(31) Pin 33(29) PPWM SPWMA nPnA (pb) (pnb) (SPWMB) (nPB) (nPnB) <SERVICE STATION MOTOR> Inputs Outputs Whinny Register Bits Pin 38 (37) Pin 36(32) Pin 34(30) PPWM...
  • Page 29 CIRCUIT DESCRIPTION <5> Quarterhorse Block Diagram <Figure 18. Quarterhorse Block Diagram showing typical external components>...
  • Page 30 CIRCUIT DESCRIPTION 3.1.6 SIXSHOOTOR ASIC 3.1.6.1 General Information The Six-shooter ASIC exists for operating the Ballast Resistor and TIJ 2.0 Inkjet Head, and it has 4 head address HA [3-0], input of the 6 strobe nSTB [5-0], and output of the 48 nozzle control. 3.1.6.2 OPERATE TIMING AND INTERNAL BLOCK DIAGRAM <figure 19.
  • Page 31 CIRCUIT DESCRIPTION 3.1.6.3 Decoder Logic Truth Table nSTRB5 nSTRB4 nSTRB3 nSTRB2 nSTRB1 nSTRB0 None None...
  • Page 32 CIRCUIT DESCRIPTION 3.1.6.4 Power Driver Output Loading Schematic <Figure 21. SIXSHOOTER Power Output Loading Schematic>...
  • Page 33 CIRCUIT DESCRIPTION 3.1.7 ERTE ASIC 3.1.7.1 General Information The ERTE ASIC is driven by 19.2V, and consists of three functional blocks, such as the Head, the Pen ID which find out the kind of head by checking temperature and resistance difference when firing, and the Resistor Test which checks the possibili- ty of the head firing.
  • Page 34 CIRCUIT DESCRIPTION 3.1.8 FAX SENDING/RECEIVING PART 3.1.8.1 General Information The circuit is for managing the transmitting signals of Modem and between the LIU part and Modem. 3.1.8.2 MODEM There are two models, FM214 for the Basic model and FM 214-VS for the TAD model, which supports the Digital TAD and Speaker Phone.
  • Page 35 CIRCUIT DESCRIPTION 3.1.8.6 FM214 MODEM BLOCK DIAGRAM 3.1.8.7 FM214-VS MODEM BLOCK DIAGRAM...
  • Page 36 CIRCUIT DESCRIPTION 3.1.8.8 FM214 SERIES MODEM PIN DESCRIPTION...

  • Page 37: Basic Concept

    CIRCUIT DESCRIPTION 3.2 OPE 3.2.1 Basic Concept 3.2.1.1 Overview 3.2.1.2 UART OPE BOARD is separated from the Main Board functional- OPE and MAIN exchange information mutually by using ly, and operates entire Micom(HT48C5A-000Z) in the asynchronous communication mode(UART), and in full Board.
  • Page 38 CIRCUIT DESCRIPTION 3.2.2.2 UART communication DATA <1> UART transmission DATA(received by the Main side) Types STATUS USED PORT LEVEL REMARKS key data PORT PC0~PORT PC7 SCAN POSITION sensor PORT PB3 MAGIC not applied DOC. detector sensor PORT PB-5 MAGIC not applied For initial use of initial OPE After power on, generated only once UART communication...
  • Page 39 CIRCUIT DESCRIPTION <2> Received DATA(transmitted by MAIN) 1. DATA TYPE DATA types Meaning Remarks a1 H LCD DISPLAY DATA(FULL LINE) a4 H LED DATA 2. NO. OF DATA • In case DATA is N BYTE, N+1 3. DATA In case DATA TYPE is LCD DATA, it is configured with ASCII CODE to be displayed. In case DATA TYPE is LED DATA, it is 1 BYTE.
  • Page 40 CIRCUIT DESCRIPTION 3.2.3 I/O PORT configuration and use usage It has 32 I/O Ports, and 24 Ports of them are arranged to decide I/O direction with Software Control, and the rest 8 Ports are arranged to be used for Input or Output only. All of I/O Ports are classified into four Blocks according to the characteristics of I/O Control, and each Block consists of 8 Ports.
  • Page 41 CIRCUIT DESCRIPTION 3.3 LIU B’d 3.3.1 GENERAL DESCRIPTION LIU ( Line interface unit ) is consist of Tel-line interface part and FAX/Speech part. <1> TEL LINE INTERFACE PART • Surge and over voltage protection part • Remote circuit • Ring detector circuit •...
  • Page 42 CIRCUIT DESCRIPTION 3. Ring detector circuit • C9 use for DC coupling and Ring impedance ( Ring impedance spec : Min 4Kohm) • R1 ( 1/ 1W )protect overvoltage into PC814. • Ring signal transfer from 1st circuit to 2nd circuit through PC814 •...
  • Page 43 CIRCUIT DESCRIPTION <2> Fax / Speech part • Fax TX / RX circuit • Speech part ( Handset MIC / RECEIVE ) 1. FAX TX / RX circuit • DTMF / OGM (335T) and Fax tone transmit from Modem tx part → impedance matching part (R43, C35, R4) →T1 trans →...
  • Page 44 SCHEMATIC DIAGRAMS SCHEMATIC DIAGRAMS 4. Schematic Diagrams 4-1 Main Circuit Diagram (1/4) SF-330/335T -> 0ohm 2012 type SF-331P -> Bead 2012 type (BD5,BD8:600ohm, BD6,7:120ohm) Repair Manual Repair Manual Samsung Electronics Samsung Electronics...
  • Page 45 SCHEMATIC DIAGRAMS Main Circuit Diagram (2/4) FOR SF-335T 64M FOR SF-330 16M Repair Manual Samsung Electronics...
  • Page 46 SCHEMATIC DIAGRAMS Main Circuit Diagram (3/4) FOR SF-335T FOR SF-330 (for SF-335T) FM214 for SF-330/SF331P FOR SF-335T Repair Manual Samsung Electronics...
  • Page 47 SCHEMATIC DIAGRAMS Main Circuit Diagram (4/4) ERTE (ONLY 331P) (ONLY 331P) (ONLY 331P) (ONLY 331P) (ONLY 331P) Repair Manual Samsung Electronics...
  • Page 48 SCHEMATIC DIAGRAMS 4-2 LIU Circuit Diagram 2002.06.25 Repair Manual Samsung Electronics...
  • Page 49 SCHEMATIC DIAGRAMS 4-3 OPE Circuit Diagram 2002.06.03 Repair Manual Samsung Electronics...

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