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AK4115 LINE Opt out PORT2 AK4648 LINE 10pin Header PORT3 Control Data 10pin Header PORT4 AGND Figure 1. AKD4648-C Block Diagram * Circuit diagram and PCB layout are attached at the end of this manual <KM088701> 2007/04 - 1 -...
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[AKD4648-C] Evaluation Board Manual Operation sequence (1) Set up the power supply lines. (1-1) In case of using the regulator. (1-1-1) TVDD is supplied from the regulator. Set up the jumper pins. JP22 JP23 REG_SEL TVDD_SEL State Short Set up the power supply lines.
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[AKD4648-C] Evaluation mode In case of AK4648 evaluation using AK4115, it is necessary to correspond to audio interface format for AK4648 and AK4115. About AK4648’s audio interface format, refer to datasheet of AK4648. About AK4115’s audio interface format, refer to Table 2 on page 11 in this manual.
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[AKD4648-C] (1) External Slave Mode (1-1) Evaluation of A/D using DIT of AK4115 PORT2 (DIT) and X1 (X’tal) are used. DIT generates audio bi-phase signal from received data and which is output through optical connector (TOTX141). Nothing should be connected to PORT1 (DIR) and PORT3 (DSP).
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[AKD4648-C] (2) External Master Mode (2-1) Evaluation of A/D using DIT of AK4115 PORT2 (DIT) and X1 (X’tal) are used. Nothing should be connected to PORT1 (DIR) and PORT3 (DSP). In Master Mode, BICK and LRCK of AK4648 should be input to AK4115. Please refer to Table2 on page 11.
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[AKD4648-C] (3) PLL Slave Mode (3-1) Reference Clock : MCKI pin (3-1-1) Evaluation of A/D using DIT of AK4115 PORT2 (DIT) and PORT3 (DSP) are used. Nothing should be connected to PORT1 (DIR). The system clock (PLL reference clock) should be connected to MCLK of PORT3. MCKO of AK4648 should be input to AK4115’s XTI.
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[AKD4648-C] (3-2) Reference Clock : BICK or LRCK pin (3-2-1) Evaluation of A/D using DIT of AK4115 X1 (X’tal) and PORT2 (DIT) are used. Nothing should be connected to PORT1 (DIR). The jumper pins should be set as follows. JP19...
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[AKD4648-C] (3-2-4) All interface signals are fed externally PORT3 (DSP) is used. Nothing should be connected to PORT1 (DIR) and PORT2 (DIT). BICK, LRCK, and SDTI are supplied from PORT3. The jumper pins should be set as follows. JP19 JP21...
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[AKD4648-C] (4-3) All interface signals are fed externally PORT3 (DSP) is used. Nothing should be connected to PORT1 (DIR) and PORT2 (DIT). The system clock (PLL reference clock) should be connected to MCLK of PORT3. In case of supplying MCKO to DSP, the JP14 (4115_MCKI)’s lower side should be connected to MCLK of DSP.
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[AKD4648-C] DIP Switch set up [S1] (SW DIP1-4): Mode setting for AK4648 and AK4115. Name ON (“H”) OFF (“L”) Default CAD0 AK4648 Chip Address Setting: (See Table 4) OCKS1 AK4115 Master Clock Setting: (See Table 3) DIF0 AK4115 Audio Format Setting...
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[AKD4648-C] Other jumper pins set up [JP1] (GND) : Analog ground and Digital ground. SHORT : Common. (The connector “DGND” can be open.) OPEN : Separated. <Default> [JP2] : Selection of RIN3 path or PLL Mode. RIN3 : RIN3 path.
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Serial Control The AKD4648-C can be connected via the USB port with attached USB interface board. Connect PORT4 (CTRL) with PC by 10 wire flat cable packed with the AKD4648-C. Table 4 shows switch and jumper settings for serial control.
[AKD4648-C] Analog Input/Output Circuits (1) Input Circuits Input Circuits of LIN1/RIN1, LIN2/RIN2, LIN3/RIN3, LIN4/RIN4, and MIN. LIN1/RIN1 RIN1 LIN1 2.2k LIN1 2.2k RIN1 MPWR 2.2k LIN2 2.2k RIN2 LIN2/RIN2 RIN2 LIN2 RIN3 MIN/LIN3/RIN3 LIN3 JP12 MIN/LIN3 RIN4 LIN4/RIN4 LIN4 Figure 3. Input circuits LIN1/RIN1, LIN2/RIN2, LIN3/RIN3, LIN4/RIN4, and MIN <KM088701>...
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[AKD4648-C] When LIN3/RIN3 paths of AK4648 are used, JP2 and JP12 should be set as follows. AIN3 bit = “1” (Register Address 21H) JP12 LIN3 VCOC RIN3 When MIN path of AK4648 is used, JP12 should be set as follows.
[AKD4648-C] (2) Output Circuits (2-1) HP Output Circuit HPR Cap-less 220u short 220u short 0.22u 0.22u HVCM HPL Cap-less HVCM Figure 4. HP Output Circuit (2-1-1) Single-ended Mode The jumper pins should be set as follows. HPR Cap-less HPL Cap-less...
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[AKD4648-C] (2-2) LOUT/ROUT Output Circuit LOUT/ROUT ROUT open LOUT JP13 LINEOUT Figure 5. LOUT/ROUT Output Circuit The jumper pins should be set as follows. JP13 LINEOUT <KM088701> 2007/04 - 16 -...
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High SPP (2-3-3) High Power SPK Mode The jumper pins should be set as follows. JP10 JP11 High SPN High SPP ∗ AKM assumes no responsibility for the trouble when using the above circuit examples. <KM088701> 2007/04 - 17 -...
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1. Set up the AKD4648-C according to previous term. 2. Connect IBM-AT compatible PC with AKD4648-C by 10-line type flat cable via the USB port with attached USB interface board (packed with AKD4648-C). Take care of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on Windows 2000/XP.
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[AKD4648-C] Explanation of each dialog 1. [Write Dialog] : Dialog to write data by mouse operation There are dialogs corresponding to each register. Click the [Write] button corresponding to each register to set up the dialog. If you check the check box, data becomes “H”...
[AKD4648-C] 4. [Save] and [Open] 4-1. [Save] Save the current register setting data. The extension of file name is “akr”. (Operation flow) (1) Click [Save] Button. (2) Set the file name and push [Save] Button. The extension of file name is “akr”.
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[AKD4648-C] 5. [Function3 Dialog] The sequence of register setting can be set and executed. (1) Click [F3] Button. (2) Set the control sequence. Set the address, Data and Interval time. Set “-1” to the address of the step where the sequence should be paused.
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[AKD4648-C] 6. [Function4 Dialog] The sequence that is created on [Function3] can be assigned to buttons and executed. When [F4] button is clicked, window as shown in Figure 8 opens. Figure 8. [F4] window <KM088701> 2007/04 - 22 -...
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[AKD4648-C] 6-1. [OPEN] buttons on left side and [START] buttons (1) Click [OPEN] button and select the sequence file (*.aks). The sequence file name is displayed as shown in Figure 9. Figure 9. [F4] window(2) (2) Click [START] button, then the sequence is executed.
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[AKD4648-C] 7. [Function5 Dialog] The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. When [F5] button is clicked, the following window as shown in Figure 10 opens. Figure 10. [F5] window 7-1.
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[AKD4648-C] Figure 11. [F5] windows(2) 7-2. [SAVE] and [OPEN] buttons on right side [SAVE] : The register setting file names assign can be saved. The file name is *.ak5 [OPEN] : The register setting file names assign that are saved in *.ak5 are loaded.
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[AKD4648-C] 8. [Filter Dialog] This dialog can easily set the AK4648’s programmable filter. Figure 12. [Filter] window 8-1. Value input columns on left side [Sampling Rate] Input value of sampling frequency [unit : Hz] <default : 44100> [Cut Off Frequency of FIL1] Input value of cut off frequency of FIL1 [unit : Hz] <default : 150>...
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[AKD4648-C] 9. [5 Band EQ Dialog] This dialog can easily set the AK4648’s 5-Band Equalizer. Figure 13. [5 Band EQ] window When the check box of “5 Band EQ” is checked, 5-Band Equalizer is ON (FBEQ bit = ”1”). When the slide button is changed, its value is written to the internal register immediately.
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[AKD4648-C] AK4648 LIN2/RIN2 => ADC (MGAIN+20dB) FFT fs=44.1kHz, No Signal -100 -110 -120 -130 -140 Figure 20. FFT Plot (No signal) AK4648 LIN2/RIN2=>ADC (MGAIN+20dB) Crosstalk, fs=44.1kHz, -1dB Input, red R=>L, blue L=>R T T T T T T T T T T T...
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[AKD4648-C] 2-2 ADC (LIN2/RIN2 ADC)(MIC-Amp Gain:0dB) AK4648 LIN2/RIN2 => ADC (MGAIN 0dB) THD + N vs Input Level , fs=44.1kHz, fin=1kHz -100 -100 Figure 22. THD+N vs. Input Level AK4648 LIN2/RIN2 => ADC (MGAIN 0dB) THD + N vs Input Frequency, fs=44.1kHz, -1dB Input -100 Figure 23.
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[AKD4648-C] AK4648 DAC => LINEOUT FFT, fs=44.1kHz, No Signal -100 -110 -120 -130 -140 Figure 36. FFT Plot (No signal) AK4648 DAC => LINEOUT Crosstalk, fs=44.1kHz, 0dB Input, red R=>L, blue L=>R T T T T T T -100 -102...
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[AKD4648-C] 2-4 DAC (DAC HP(Single-ended Mode))(HPG=0dB) AK4648 DAC =>HP (Single-end) THD + N vs Input Level , fs=44.1kHz, fin=1kHz -100 -120 -110 -100 dBFS Figure 38. THD+N vs. Input Level AK4648 DAC =>HP (Single-end) THD + N vs Input Frequency, fs=44.1kHz, 0dB Input -100 Figure 39.
[AKD4648-C] Revision History Date Manual Board Reason Contents (YY/MM/DD) Revision Revision First 07/03/19 KM088700 Edition Parts 07/04/13 KM088701 AK4648 Rev.A → Rev.B Change IMPORTANT NOTICE • These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei EMD Corporation (EMD) sales office or authorized distributor concerning their current status.
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0.1u 0.1u 2.2u 2.2u VCOM RIN2 RIN1/IN1+ RIN2/IN2- RIN1 AGND HVDD AGND 0.1u 0.1u Title Title Title AKD4648-C AKD4648-C AKD4648-C AGND Size Size Size Document Number Document Number Document Number AK4648 AK4648 AK4648 Date: Date: Date: Friday, March 30, 2007...
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LOUT/ROUT RIN4 ROUT LIN4/RIN4 LIN4/RIN4 open open LIN4 LOUT JP13 JP13 LINEOUT LINEOUT Title Title Title AKD4648-C AKD4648-C AKD4648-C Size Size Size Document Number Document Number Document Number Input/Output Input/Output Input/Output Date: Date: Date: Friday, March 30, 2007 Friday, March 30, 2007...
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0.1u 0.1u 4115_MCKI 4115_MCKI PORT2 PORT2 JP14 JP14 MCKO TOTX141 TOTX141 0.1u 0.1u Title Title Title AKD4648-C AKD4648-C AKD4648-C Size Size Size Document Number Document Number Document Number DIR/DIT DIR/DIT DIR/DIT Date: Date: Date: Friday, March 30, 2007 Friday, March 30, 2007...
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SDTO-IN SDTO JP21 JP21 SDTI SDTI 0.1u 0.1u DIR_SDTO 74HC14 74HC14 0.1u 0.1u Title Title Title AKD4648-C AKD4648-C AKD4648-C Size Size Size Document Number Document Number Document Number LOGIC LOGIC LOGIC Date: Date: Date: Friday, March 30, 2007 Friday, March 30, 2007...
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TVDD-SEL TVDD-SEL (short) (short) TVDD1 TVDD1 TVDD T45_OR T45_OR DGND1 DGND1 T45_BK T45_BK Title Title Title AKD4648-C AKD4648-C AKD4648-C Size Size Size Document Number Document Number Document Number POWER POWER POWER Date: Date: Date: Friday, March 30, 2007 Friday, March 30, 2007...
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