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AKM AKD4633-A Manual

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ASAHI KASEI
AKD4633-A is an evaluation board for the AK4633VN, 16bit mono CODEC with MIC/SPK amplifier. The
AKD4633-A can evaluate A/D converter and D/A converter separately in addition to loopback mode (A/D
 D/A). AKD4633-A also has the digital audio interface and can achieve the interface with digital audio
systems via opt-connector.
 Ordering guide
AKD4633-A
 DIT/DIR with optical input/output
 BNC connector for an external clock input
 10pin Header for serial control mode
5V
3.3V
Regulator
MIC-Jack
MIC
BEEP/MIN/MOUT
AOUT
SPK-Jack
* Circuit diagram and PCB layout are attached at the end of this manual.
<KM079407>
GENERAL DESCRIPTION
--- Evaluation board for AK4633VN
(Cable for connecting with an USB port and control software is packed with this.)
AVDD
DVDD
SVDD
AK4633VN
Figure 1. AKD4633-A Block Diagram
AK4633 Evaluation board Rev.3
FUNCTION
GND
AK4114
Clock
Gen
- 1 -
AKD4633-A
Control Data
10pin Header
DSP
10pin Header
Opt In
Opt Out
[AKD4633-A]
2016/10

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Summary of Contents for AKM AKD4633-A

  • Page 1 AKD4633-A is an evaluation board for the AK4633VN, 16bit mono CODEC with MIC/SPK amplifier. The AKD4633-A can evaluate A/D converter and D/A converter separately in addition to loopback mode (A/D  D/A). AKD4633-A also has the digital audio interface and can achieve the interface with digital audio systems via opt-connector.
  • Page 2 ASAHI KASEI [AKD4633-A] Evaluation Board Manual  Operation sequence 1) Set up the power supply lines. 1-1) When AVDD, DVDD, SVDD, and VCC are supplied from the regulator. (AVDD, DVDD, SVDD, and VCC jack should be open.). See “Other jumper pins set up (page 10)”. <default>...
  • Page 3 ASAHI KASEI [AKD4633-A] (1) Evaluation of loop-back mode (A/D  D/A) : PLL, Master Mode a) Set up jumper pins of MCKI clock X’tal of 11.2896MHz, 12MHz, 12.288MHz, 13MHz, 24MHz or 27MHz can be set in X2. X’tal of 12.288MHz (Default) is set on the AKD4633VN.
  • Page 4 Set up jumper pins of MCKI clock X’tal of 12.288MHz (Default) is set on the AKD4633-A. In this case, the AK4633VN corresponds to PLL reference clock of 12.288MHz. In this evaluation mode, the output clock from MCKO-pin of the AK4633VN is supplied to a divider (U3: 74VHC4040), BICK and FCK clocks are generated by the divider.
  • Page 5 ASAHI KASEI [AKD4633-A] (3) Evaluation of loop-back mode (A/D  D/A) : PLL, Slave Mode (PLL Reference CLOCK: BICK or FCK pin) a) Set up jumper pins of BICK clock When an external clock through a RCA connector J8 (EXT/BICK) is supplied, select EXT on JP19 (MCLK_SEL) and short JP17 (XTE).
  • Page 6 ASAHI KASEI [AKD4633-A] b) Set up jumper pins of FCK clock When an external clock through a RCA connector J9 (FCK) is supplied, select EXT on JP22 (FCK_SEL). JP24 (EXT2) and R27 should be properly selected in order to match the output impedance of the clock generator.
  • Page 7 ASAHI KASEI [AKD4633-A] (4) Evaluation of using DIR of AK4114 (opt-connector) : EXT, Slave Mode a) Set up jumper pins of MCKI clock JP17 JP18 JP21 MCLK_SEL MKFS MCKI 256fs 512fs 1024fs XTL DIR EXT b) Set up jumper pins of BICK clock...
  • Page 8 ASAHI KASEI [AKD4633-A] (5) Evaluation of using DIT of AK4114 (opt-connector) : EXT, Slave Mode a) Set up jumper pins of MCKI clock JP17 JP18 JP21 MKFS MCLK_SEL MCKI 256fs 512fs 1024fs XTL DIR EXT b) Set up jumper pins of BICK clock...
  • Page 9 ASAHI KASEI [AKD4633-A]  DIP Switch set up [SW3] (MODE) : Mode Setting of AK4633-VN and AK4114 ON is “H”, OFF is “L”. Name ON (“H”) OFF (“L”) DIF0 AK4114 Audio Format Setting DIF1 See Table 2 DIF2 Clock Operation Mode select...
  • Page 10 ASAHI KASEI [AKD4633-A]  Other jumper pins set up 1. JP1 (GND) : Analog ground and Digital ground OPEN : Separated. SHORT : Common. (The connector “DGND” can be open.) <Default> 2. JP2 (MICP) : Connection between MICP pin and BEEP pin of the AK4633VN.
  • Page 11 The AKD4633-A should be connected to a PC (IBM-AT compatible) via a USB control box (AKDUSBIF-B) included in this package. The USB control box is connected to a PC with a USB cable and the AKD4633-A with a 10-pin flat cable.
  • Page 12 ASAHI KASEI [AKD4633-A]  Analog Input / Output Circuits (1) Input Circuits a) MIC Input Circuit MIC-JACK JP12 AVSS JACK MIC_SEL MR-552LS AVSS Figure 3. MIC Input Circuit (a-1) Analog signal is input to MIC pin via J1 connector. JP12...
  • Page 13 ASAHI KASEI [AKD4633-A] (2) Output Circuits a) AOUT Output Circuit AOUT AOUT MR-552LS AVSS AVSS Figure 5. AOUT Output Circuit b) SPK Output Circuit Note. When mini-jack is inserted or pulled out J2 (SPK-JACK) connector, JP13 (SPP_SEL) and JP14 (SPN_SEL) should be open, or “PMSPK bit” in the AK4633VN should be set to “0”.
  • Page 14 (b-3) Analog signal of SPP/SPN pins are output from “Dynamic Speaker” on the evaluation (SPK1). JP13 JP14 JP31 SPN_SEL SPP_SEL Dynamic Dynamic Dynamic(EXT) Dynamic Dynamic(EXT) Piezo(EXT) Piezo(EXT)  AKM assumes no responsibility for the trouble when using the above circuit examples. <KM079407> 2016/10 - 14 -...
  • Page 15 ASAHI KASEI [AKD4633-A] Control Software Manual  Evaluation Board and Control Software Settings 1. Set up the evaluation board as needed, according to the previous terms. 2. Connect the evaluation board and PC with a USB cable. 3. The USB control is recognized as HID (Human Interface Device) on the PC.
  • Page 16 ASAHI KASEI [AKD4633-A]  Operation Overview Function and Register map are controlled by this control software. These controls may be selected by the upper tabs. Frequently used buttons, such as the register initializing button “Write Default”, are located outside of the switching tab window.
  • Page 17 ASAHI KASEI [AKD4633-A]  Tab Functions (1) [Function] Tab: Function Control Sequence operation and a setup of a register are executed with the function button arranged at the upper part, and each button in a block diagram. Figure 8. [Function] Window Function block : Executes a sequential process shown on each button.
  • Page 18 ASAHI KASEI [AKD4633-A] (1-1) Function block Figure 9. [Function] Block A function button executes the sequence process shown on the each button and updates several registers. These functions are mainly for path settings. Function Name Description Input Output Path MIC-ADC...
  • Page 19 ASAHI KASEI [AKD4633-A] ] Sequential process (1-1-1) MIC-ADC When [MIC-ADC] button in the main window is clicked, the sequence for MIC input Settings is executed. (Note Figure 10. [MIC-ADC] Setting (After) Note 4. The function button makes some block power up, but [Power Down/Up] button is not changed.
  • Page 20 ASAHI KASEI [AKD4633-A] (1-1-2) [AIN-ADC] Sequential process When [AIN-ADC] button in the main window is clicked, the sequence for Analog line input Settings is executed. (Note Figure 11. [AIN-ADC] Setting (After) <KM079407> 2016/10 - 20 -...
  • Page 21 ASAHI KASEI [AKD4633-A] (1-1-3) [DAC-Speaker] Sequential process When [DAC-SPK] button in the main window is clicked, the sequence for Speaker output Settings is executed. (Note Figure 12. [DAC-SPK] Setting (After) <KM079407> 2016/10 - 21 -...
  • Page 22 ASAHI KASEI [AKD4633-A] (1-1-4) [DAC-AOUT] Sequential process When [DAC-AOUT] button in the main window is clicked, the sequence for Line output Settings is executed. (Note Figure 13. [DAC-AOUT] Setting (After) <KM079407> 2016/10 - 22 -...
  • Page 23 ASAHI KASEI [AKD4633-A] Path and Various Setting Block (1-2) The enabled paths are shown. The FS and PLL bits, etc… can be set up. [Input_ADC Setting], [Digital Filter Setting], [ALC Setting], [DAC_Output Setting] -- each setting dialog can be opened.
  • Page 24 ASAHI KASEI [AKD4633-A] Recording: [Power Down/Up] Button Register bit Setup value Power Up PMVCM “1” (Note PMPFIL When PFSDO bit = 1, PMPFIL bit = 1 PMADC “1” Power Down PMADC “0” PMPFIL “0” (Note Playback: [Power Down/Up] Button Register bit...
  • Page 25 ASAHI KASEI [AKD4633-A] (2) [REG] Tab: Register Map This tab is for register write. Each bit on the register map is a push-button switch. The register is updated by mouse operation. Button Down indicates “1” and the bit name is shown in red (when read-only the name is shown in dark red).
  • Page 26 ASAHI KASEI [AKD4633-A] [Write]: Data Write Dialog (2-1) Select the [Write] button located on the right of the each corresponding address when changing two or more bits on the same address simultaneously. Click the [Write] button located on the right of the each corresponded address for a pop-up dialog box.
  • Page 27 ASAHI KASEI [AKD4633-A]  Dialog Box (1) [Save]: [Save Address of Register] Dialog Box Click the [Save] button in the main window for save address setting dialog box. Figure 17. [Save] Window [All Address] check box : When the [All Address] checkbox is checked, all register settings will be saved.
  • Page 28 ASAHI KASEI [AKD4633-A] (2) [All Reg Write]: [All Register Write] Dialog Box Click the [All Reg Write] button in the main window to open register setting file window show below. Register setting files saved by the [Save] button may be applied.
  • Page 29 ASAHI KASEI [AKD4633-A] (3) [Sequence]: [Sequence] Dialog Box Click the [Sequence] button in the main window to open register sequence setting dialog box. Register sequence can be set in this dialog box. Figure 19. [Sequence] Window ~ Sequence Setting ~ Set register sequence according to the following process.
  • Page 30 ASAHI KASEI [AKD4633-A] Input sequence [Address] : Data address [Data] : Write data [Mask] : Mask This value “ANDed” with the write data becomes the input data. The bits which corresponding Mask bit = “0” are not changed. At this time, data read is not executed, and the storage data of this software is used.
  • Page 31 ASAHI KASEI [AKD4633-A] (4) [Sequence (File)]: [Sequence by *.aks file] Dialog Box Click the [Sequence (File)] button to open sequence setting file dialog box shown below. Files saved in the “Sequence setting dialog” can be applied in this dialog. Figure 20. [Sequence (File)] Window [Open (left)] button : Opens a sequence setting file (*.aks).
  • Page 32 ASAHI KASEI [AKD4633-A] (5) [Input_ADC Setting]: [Input_ADC Setting] Dialog Box Click the [Input_ADC Setting] button in the main window to open MIC and ADC setting dialog. The settings on this dialog are interlocked with the settings on register map. (Refer to the datasheet for register definitions.) Figure 22.
  • Page 33 ASAHI KASEI [AKD4633-A] (6) [Digital Filter Setting]: [Filter Setting] Dialog Box Click the [Digital Filter Setting] button in the main window to open digital filter setting dialog. Coefficient and frequency of digital filter are calculated on this dialog. (Refer to the datasheet for register definitions.) Figure 24.
  • Page 34 ASAHI KASEI [AKD4633-A] (6-1) Parameter Setting “HPF Enable(HPFAD bit)”, “HPF Enable(HPF bit)”, “EQ1”, “EQ2” Please set ON/OFF of Filter with a check button. When checked it, Filter becomes ON. When “Notch Filter Auto Correction” is checked, perform automatic correction of the center frequency of the notch filter is executed.
  • Page 35 ASAHI KASEI [AKD4633-A] (6-2) [Register Setting]: [Register Setting for Filter] Dialog Box Click the [Register Setting] button, a register set value is displayed. Figure 26. [Register Setting for Filter] Window Followings are the cases when a register set value is updated.
  • Page 36 ASAHI KASEI [AKD4633-A] (6-3) [F Response]: [Filter Plot] Dialog Box The frequency response of digital filter is displayed when push a [F Response] button. Then, the register setting for digital filter are also updated. Change Frequency Range, and indication of a frequency characteristic is updated when push a [UpDate] button.
  • Page 37 ASAHI KASEI [AKD4633-A] (6-4) 2-BandEQ operation on Filter Plot screen When EQ (1,2) is turning “ON”, a green number is displayed on the Filter Plot dialog box. This number shows the setting of the center frequency and the gain of each EQ.
  • Page 38 ASAHI KASEI [AKD4633-A] (6-5) About “Notch Auto Correct” If the gain of 2-Band EQ is set to “-1”, Equalizer becomes a notch filter. When the center frequency of two or more notch filters is adjacent, the gap is generated in the center frequency.
  • Page 39 ASAHI KASEI [AKD4633-A] (7) [ALC Setting]: [ALC Setting] Dialog Box Click the [ALC Setting] button in the main window to open ALC setting dialog. ALC parameters are controlled in this dialog. The settings on this dialog are interlocked with the settings on register map.
  • Page 40 ASAHI KASEI [AKD4633-A] (8) [DAC_Output Setting]: [DAC_Output Setting] Dialog Box Click the [DAC Output Setting] button in the main window to open DAC setting dialog. Output mode, DAC and output gain setting are available. The settings on this dialog are interlocked with the settings on register map.
  • Page 41 ASAHI KASEI [AKD4633-A] Revision History Date Manual Board Reason Page Contents Revision Revision 05/07/14 KM079400 First Edition 05/08/23 KM079401 Update Change of a figure & circuit 05/09/16 KM079402 Error Port Numbers are corrected in circuit. Correct 05/10/21 KM079403 Update Device revision of AK4633 is changed to “Rev.B”.
  • Page 42 AKM or any third party with respect to the information in this document. You are fully responsible for use of such information contained in this document in your product design or applications.
  • Page 43 LVC_SEL LVC_SEL AVSS JP11 JP11 VCC3.3V VCC_SEL VCC_SEL 32pin_2 32pin_2 D3.3V (short) (short) Title Title Title AKD4633-A AKD4633-A AKD4633-A Size Size Size Document Number Document Number Document Number AK4633-VN AK4633-VN AK4633-VN Date: Date: Date: Friday, March 30, 2007 Friday, March 30, 2007...
  • Page 44 DIODE ZENER SPP_SEL SPP_SEL MR-552LS MR-552LS AVSS AVSS AOUT AOUT MR-552LS MR-552LS AVSS AVSS Title Title Title AKD4633-A AKD4633-A AKD4633-A Size Size Size Document Number Document Number Document Number Input/Output Input/Output Input/Output Date: Date: Date: Thursday, February 15, 2007 Thursday, February 15, 2007...
  • Page 45 MR-552LS AVSS JP23 JP23 EXT1 EXT1 MR-552LS MR-552LS AVSS JP24 JP24 EXT2 EXT2 Title Title Title AKD4633-A AKD4633-A AKD4633-A Size Size Size Document Number Document Number Document Number CLOCK CLOCK CLOCK Date: Date: Date: Thursday, February 15, 2007 Thursday, February 15, 2007...
  • Page 46 MCKO_SEL MCKO2 DIR_MCLK MCKO1 D3.3V D3.3V PORT2 PORT2 D3.3V TOTX141 TOTX141 0.1u 0.1u Title Title Title AKD4633-A AKD4633-A AKD4633-A Size Size Size Document Number Document Number Document Number DIR/DIT DIR/DIT DIR/DIT Date: Date: Date: Thursday, February 15, 2007 Thursday, February 15, 2007...
  • Page 47 0.1u 74HCU04 74HCU04 74HC04 74HC04 74HC04 74HC04 74HC14 74HC14 74HC14 74HC14 U10D U10D U10A U10A Title Title Title AKD4633-A AKD4633-A AKD4633-A 74HC04 74HC04 74HC04 74HC04 74HCU04 74HCU04 74HC14 74HC14 74HC14 74HC14 Size Size Size Document Number Document Number Document Number...
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