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AKM AKD4103A-B Manual

Akd4103a evaluation board
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The AKD4103A-B is an evaluation board for the AK4103A, 192kHz DIT. The AKD4103A-B has the interface
with AKM's A/D converter evaluation boards and AKM's DIR evaluation boards. Therefore, it is easy to evaluate
the AK4103A. The AKD4103A-B also has the digital audio interface and can achieve the interface with digital
audio systems via BNC unbalance or XLR balance connector.
 Ordering guide
AKD4103A-B ---
 Digital interface
 Compatible with 2 types of interface
- Direct interface with AKM's ADC, DIR evaluation boards by 10pin header
- BNC/XLR output
 Serial control data I/F
- 1 input/output port (10-pin port)
TX
*Circuit diagram and PCB layout are attached at the end of this manual.
<KM076804>
AK4103A Evaluation Board Rev.1
GENERAL DESCRIPTION
Evaluation board for AK4103A
(Control software is packed with this.)
FUNCTION
C,U,V
Figure 1. AKD4103A-B Block Diagram
GND
5V
AK4103A
Serial Data in
- 1 -
[AKD4103A-B]
AKD4103A-B
Control
(For DIT)
2015/08

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Summary of Contents for AKM AKD4103A-B

  • Page 1 AKM’s A/D converter evaluation boards and AKM’s DIR evaluation boards. Therefore, it is easy to evaluate the AK4103A. The AKD4103A-B also has the digital audio interface and can achieve the interface with digital audio systems via BNC unbalance or XLR balance connector.

  • Page 2: Evaluation Board Manual

    (DIT) DAUX DAUX AKD4103A-B MCLK, BICK, LRCK and SDTI are input the via 10pin header (PORT5: DIT). The AKD4103A-B can be connected with the AKM’s DAC evaluation board via 10-line cable. Set-up of a Bi-phase output signal Connector JP19 (TXP)
  • Page 3 [AKD4103A-B] CKS1 pin CKS0 pin (SW3_5) (Sub_JP19) MCLK fs (max) CKS1 bit CKS0 bit 128fs 28k-192 kHz Default 256fs 28k-108 kHz 384fs 28k-54 kHz 512fs 28k-54 kHz Table 3. Master Clock Frequency Select b-1. Set-up of input/output of BICK and LRCK...

  • Page 4: Serial Control

    At asynchronous mode (ANS=0), the AK4103A can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT6 (uP-I/F) with PC by 10-line flat cable packed with the AKD4103A-B. Take care of the direction of connector. There is a mark at pin#1. The pin layout of PORT6 is shown in Figure 3.

  • Page 5: Jumper Setup

    [AKD4103A-B]  Toggle switch set-up Reset switch for AK4103A. Set to “H” during normal operation. Bring to “L” once after the power is supplied.  DIP switch (SW1) set-up: -off- means “L” Switch Name Function Default IPS0 Don’t care DIF0 Set-up of DIF0 pin.
  • Page 6 [AKD4103A-B] Control Soft Manual  Evaluation Board and Control Soft Settings 1. Set an evaluation board properly. 2. Connect a USB control box (AKUSBIF-B) and an evaluation board. Pay attention about direction of the 10pin header when connecting to an AKUSBIF-B.

  • Page 7: Operation Overview

    [AKD4103A-B] ■Operation Overview Function, register map and testing tool can be controlled by this control soft. These controls are selected by upper tabs. Buttons which are frequently used such as register initializing button “Write Default”, are located outside of the switching tab window.
  • Page 8 [AKD4103A-B] ■Dialog Boxes [All Req Write] Click [All Reg Write] button in the main window to open register setting files. Register setting files saved by [SAVE] button can be applied. Figure 5. Window of [ All Reg Write] [Open (left)] : Selecting a register setting file (*.akr).
  • Page 9 [AKD4103A-B] [Data R/W] Click the [Data R/W] button in the main window for data read/write dialog box. Data write is available to specified address. Figure 6. Window of [ Data R/W ] Address Box : Input data address in hexadecimal numbers for data writing.
  • Page 10 [AKD4103A-B] [Sequence] Click [Sequence] button to open register sequence setting dialog box. Register sequence can be set in this dialog box. Figure 7. Window of [ Sequence ] Sequence Setting Set register sequence by following process bellow. (1)Select a command Use [Select] pull-down box to choose commands.

  • Page 11: Control Buttons

    [AKD4103A-B] Valid boxes for each process command are shown bellow. · No_use : None · Register : [Address], [Data], [Interval] · Reg(Mask) : [Address], [Data], [Mask], [Interval] · Interval : [Interval] · Stop : None · End : None Control Buttons The function of Control Button is shown bellow.
  • Page 12 [AKD4103A-B] [Sequence(File)] Click [Sequence(File)] button to open sequence setting file dialog box. Those files saved in the “Sequence setting dialog” can be applied in this dialog. Figure 8. Window of [ Sequence(File) ] [Open (left)] : Opening a sequence setting file (*.aks).

  • Page 13: Reg]: Register Map

    [AKD4103A-B] 1. [REG]: Register Map This tab is for a register writing and reading. Each bit on the register map is a push-button switch. Button Down indicates “H” or “1” and the bit name is in red (when read only it is in deep red).
  • Page 14 [AKD4103A-B] [Write]: Data Writing Dialog It is for when changing two or more bits on the same address at the same time. Click [Write] button located on the right of the each corresponded address for a pop-up dialog box. When checking the checkbox, the register will be “H” or “1”, when not checking the register will be “L” or ”0”.

  • Page 15: Revision History

    [AKD4103A-B] Revision History Date Manual Board Reason Page Contents (yy/mm/dd) Revision Revision 04/11/22 KM076800 First edition 05/11/21 KM076801 Modification Block diagram at DIT Evaluation was added. “Control Soft Manual” was changed. 6-14 10/03/05 KM076802 Change “Control Soft Manual” was changed.

  • Page 16: Important Notice

    AKM or any third party with respect to the information in this document. You are fully responsible for use of such information contained in this document in your product design or applications.
  • Page 17 CKS1 CKS1 JP19 FS2/CCLK CKS0 CKS0 FS3/CDTO FS3/CDTO JP20 AK4103A DIF2 DIF1 DIF0 Title Title Title AKD4103A-B AKD4103A-B AKD4103A-B Size Size Size Document Number Document Number Document Number AKD4103A-B-SUB AKD4103A-B-SUB AKD4103A-B-SUB - 17- Date: Date: Date: Tuesday, August 11, 2015...
  • Page 18 EMCK2 DAUX1 DAUX2 SW 2 0.1u MCKO1 74LVC157 MCKO2 OVDD OVDD BICK SDTO LRCK Title Title Title AKD4103A-B AKD4103A-B AKD4103A-B - 18- Size Size Size Document Number Document Number Document Number MAIN MAIN MAIN Date: Date: Date: Tuesday, August 11, 2015...
  • Page 19 OCKS0/FS0 PSEL PSEL XTL0/CKS1 XTL1/TRANS D3V/VD XTL0 DIR_I/O DIT_I/O XTL1 74LS07 74LS07 74LS07 DIR_I/O DIT_I/O Title Title Title AKD4103A-B AKD4103A-B AKD4103A-B - 19- 74LS07 74LS07 Size Size Size Document Number Document Number Document Number MAIN MAIN MAIN Date: Date: Date:...
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