Radio Shack TRS-80 Service Manual page 47

5-Meg Hard Disk Service Manual
includes an 8-bit bidirectional data bus
(U70)
and
8
address
lines (U71). For
systems using interrupts and/or
DMA,
the
controller also provides Interrupt Request (HDBINTRQ*) and
Data Request (HDBDRQ*).
Accessing the controller
is
like other
I/O
devices
.
Address
decoding
is
done on the controller board by
U69.
This decode
can be jumpered to recognize four different address ranges
.
Standard setting
is
jumpered from
17
to
19,
which utilizes
port locations CO
to
CF
HEX*
Further decoding to allow
access
of
specific ports
is
done by
U66, U67,
and
U68.
Data
bus
direction
is
determined by
U56,
using standard bus
as
well
as
decoded signals.
Wait Enable
The
generation
of the WAIT* signal
is
controlled by
a
bit in
the MAC latch
(U29)
called Wait Enable
(WAEN*).
If
the
controller
is
ready
to
accept random access
to its
task
file, WAEN* will be asserted. After WAEN*
is
clocked through
a
latch
(U43)
to
insure WAIT*
is
not asserted during
a
bus
access
in
progress
,
DCRCS*
(BIC or BOC in
some applications)
causes WAIT* to be
asserted
to the bus*
The WAIT* line
is
released on the trailing edge of any
Read
or
Write Strobe
to
the communications latch,
U60.
This
release
is
caused by the logical OR
of RDG*
and WRG* on U38
which presets the wait
latch, U43, to
a
non-wait request
condition*
Interrupts and DRQ's
The
controller produces INTRQ*
to
signal the end
of all
disk
operations and DRQ's
to
signal data ready
to
DMA
controllers. INTRQ* and DRQ* originate on the MFM generator
(U5)
as an
auxiliary function of that chip*
The INTRQ*
signal
is
set using INTCLK and the the DRQ signal
is
set
using DRQCLK, both
of
which are produced by
U44.
Interrupts
are cleared by
CSAC*
(a
200
nanosecond version of the CSAC
signal) and AO, Al
whenever the host reads the status
register, issues
a
command or
accesses the sector number
register. Data requests (DRQ's) are cleared when the host
accesses the data or cylinder low registers DRQ's will be
reissued
for
each byte
to be
transferred. During power on or
Master Resets
(MR*),
INTRQ*
is
set and DRQ
is
reset.
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