Radio Shack TRS-80 Service Manual page 32

5-Meg Hard Disk
Service Manual
voltage reference
is
provided
to
produce bias
to an external
pass transistor
(Q2)
which drops Vcc
to the 8X300
to
approximately
+3
volts
.
All signals into and out of the
8X300 are internally level shifted
to be TTL compatible.
Read and Write Ports
Throughout
the circuit, output ports are formed by
"D"
type
latches using write strobes
(WRO -WR7) to
latch data into
the ports. Reading of ports
is
universally accomplished by
using read strobes
(RDO, RD2
,
RD4 - RD6) that enable
selected tri-state output devices
on the I/O bus.
Additionally, two read strobes are used
to clock the host
DRQ* and INTRQ* latches
(U5)
and one read strobe
is
left
unused
as
a
"dummy" port for glitch-free operation
of the
Fast
10
port decoders.
Read/Write Memory
Since the 8X300 does not permit data
to be saved
or
retrieved from dedicated program storage, RAM must be
installed
on the 10 bus.
RAM must
be accessed just like
other port accesses via the
10
bus by
10
instructions. To
provide
for addressing the RAM, three latch/counters
(U26,
U27, U28)
are connected
to the
10
bus to receive and store
addresses required
to
access the RAM (U17,U18).
RAM Addressing
The
RAM address
bus (RAO -
RA9
)
uniquely addresses one
of
1024
memory locations.
As each counter chip reaches
a
count
of
0,
it
will set
a
borrow condition
to the next higher
counter which will
be
decremented
at the end
of the
next
access
to RAM.
When all bits
of the address have been reset,
the R0VF* bit on the last counter
(U26)
will
be reset,
providing overflow status which can
be read by the processor
on (U26). By setting various beginning address values, R0VF*
can be used
to
mark the end
of
any RAM access loop from
1
to
1024 bytes
in
length. The controller board
uses this
function
to set sector buffer lengths
of 128,
256,
or 512
bytes.
Sector Buffering
All data read from or written to the disk
is
passed through
the
RAM
to
provide buffering required
for
asynchronous data
transfer between the host and disk. The counters are
post-decremented, which means that the effective addresses
are stable
to the
RAM by
at least the instruction prior
to
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