Radio Shack TRS-80 Service Manual page 31

5-Meg Hard Disk
Service Manual
(WC) is a
signal which determines the direction
of the
data
to
and from peripherals
.
When WC
is
false (during the first
half cycle)
*
data
is
being input to the
8X300 from the
10
bus.
When WC
is
true (during the second half cycle* data
is
being output to the 10 bus from the 8X300
.
Select Control
(SO
becomes active during the second half cycle instead
of
WC
if
the 10 bus contains an 8-bit 10 address
.
the WC and
SC
signals are combined by
a
NOR gate
(U33)
to
initiate all
accesses from the 8X300
to
any output port within one
instruction instead
of
the normal 5-bit immediate moves
provided
for by the
instruction set.
All instruction fetches occur late in
the second cycle of
the
preceding instruction* This time
is
marked by the
generation
of
a 65 ns
(nominal)
active high pulse called
MCLK which occurs every instruction
.
MCLK
is
used
to
latch
data prior
to
being input on the
10
bus to ensure stability
during reads* MCLK
is
also used to
disqualify read strobes
which would otherwise remain true into the second clock
cycle of any
instruction which does not write to a port.
There are two more bus control signals produced by the
8X300,
Left Bank select
(LB*)
and Right Bank select (RB*).
However* due to the
implementation of the Fast
10
Select
logic*
only
RB*
*
which
is
used
as
the chief enable signal
for U17 and U18*
is
needed.
Reset Circuit
The 8X300
is
held reset for
approximately
40
milliseconds
after initial power-on. This
is
accomplished by
an RC
network
(R42
and C52). After this power-up sequence* there
are two ways
to
reset the processor* both of
which are
controlled by the host computer.
One method
of
resetting the processor
is
by resetting of the
host
(i.e.*
reset switch) which drives the signal HDMR*
low.
The other method of resetting the processor
is
by software
control. This
is
accomplished by setting bit D4 of
port
Cl
HEX.
This latches the signal (SFTRESET) which
in
turn
triggers
a
one-shot U76 to
drive RESET*
low.
The one-shot
duration
is
set for
approximately 100 u sec
pulse width.
RESET*
is
used
to
clear the drive control latches U62 and
U52 and the host
interface WAIT*
(U43).
Processor Power Supply
Power
is
supplied to the
8X300 from the
+5
volt
(Vcc)
power
bus.
Due to the internal operation of the 8X300* an on-chip
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