Radio Shack TRS-80 Service Manual page 40

5-Meg Hard Disk
Service Manual
Due to the
circuitry associated with
the VCO to
RCLK
divider, the RDAT* output of the data separator
(U13
- 8)
will
be
high and the CLKS* output
(U12
- 8)
will
be low*
RCLK* will be the shifting clock for RDAT* and RCLK will be
the
shifting clock for CLKS*
.
These four signals are routed
into the
AM detector
.
Inside the AM detector
,
RDAT*
is
shifted into an 8-bit
synchronous serial shift register and
clocked on the
falling edge
of
RCLK*
.
CLKS*
is
shifted into
a
similar shift register on the falling edge
of RCLK*
The
output stage of the RDAT*
register
is
dumped into an
B
Al
s
comparator and the output stage of the
CLKS* register
is
dumped into
a 'OA'
comparator. AM detection occurs when both
detectors are true,
thereby setting the AMDET* latch. At the
instant AM occurs, the exact relationship between data and
clocks
is
known. It
is
also known that data
is
being clocked
by RCLK* so
CLKS* can actually be discarded? their purpose
was
in
detecting
AM*
The AMDET* signal
is
used
as a
synchronization signal to
start subsequent conversion
circuitry. The AMDET* signal remains true until the
processor again de-asserts the Search control line*
Serial to
Parallel Conversion
After
an
AM has
been detected, the serial-to-parallel
convertor
(U9)
takes over. NRZ data and RCLK are used
to
shift data bits into an 8-bit serial-to-parallel shift
register. As each bit
is
shifted,
a
divide-by-8 counter
circuit
is
incremented. After every eighth bit
of
data
is
shifted, the counter produces an overflow pulse marking byte
boundaries
in
the serial data stream. The
overflow bit from
the counter resets the counter, clocks the
data from the
shift register into an 8-bit parallel latch, and sets
a
tri-state flag register called BDONE. The flag can be read
by the
processor
to see if
any converted data
is
ready
to be
read from the latches.
When the processor sees BDONE
in
the true state, it
services
the
device by gating data onto
the 10 bus using read strobe
4
(RD4*) in
conjunction with
a
tri-state buffer
(U8).
The
act of reading the latches also clears off the pending BDONE
flag. As
successive bytes are processed, the BDONE
is
serviced by
the
processor
as
data becomes available.
Outputs from the serial-to-parallel device also include
SHFTCLK* and DOUT. SHFTCLK*
is
actually RCLK* propagated
through the device. DOUT is
the
Q
output
of the
last stage
of
the shift register string. DOUT and SHFTCLK* are routed
to
the CRC
generator checker device and also are tri-stated
38