Radio Shack TRS-80 Service Manual page 42

5-Meg Hard Disk
Service Manual
___.—
or-*,
®
for at least
250
nanoseconds during the search
for the
AM*
CRCIZ*
is
originated
on the MAC CNTRL port
(U29).
Upon
receiving the CRCIZ* signal, the CRC generator/checker will
preset all
16 of its
internal polynomial division shift
registers
to
logic ones and arm an internal latch which will
enable the checking function on the leading edge
of the
first non-zero data
to
enter the device.
It
should
be
remembered that prior
to an
AM there
is
always
a
field of
zeros (all
data bits
low) so
the first non-zero data bit
into the
device will always be the most significant bit of
the
AM
(HEX Al
)
.
The CRC device, when enabled by the first non-zero data bit,
will shift succeeding data bits into
a
feedback shift
register string with Exclusive or gates tied
to the feedback
nodes on the first, fifth, twelfth, and sixteenth registers
.
As
each RCLK occurs, the registers will divide the incoming
data and
a
unique pattern
of ones
and zeros will appear
across the registers
.
When the last bit of an ID or
data field
is
processed, the
pattern
in
the registers should be equivalent to the
16
bits
appended
to the
fields during original recording
.
The
appended bits are also entered into the CRC device.
If
all
of the bits
in
the appended field are identical to the bits
in
the registers, then the Exclusive-or-Gates
in
the
register string will have flipped all
of the ones to zeros
and the CRC will have been satisfied.
The
output
of
each register stage
is
tied to
a
16-bit
comparator which goes true when
all of its inputs are zeros.
The output
of the
comparator
is
retimed
to
remove any
decoding slivers and
is
output
as
CRCOK. The processor can
read CRCOK through U61 to see
if a
CRC error has occurred.
After the CRC bits are processed, the data stream will
contain
at
least one more byte of zeros. It
is
the
nature
of
the CRC
polynomial that
if
no
bits are set
to ones
in
the
registers and
if a
constant input
of zeros
is
shifted into
the registers, no bits will be flipped. This provides
a
convenient latching function
for the
CRCOK
flag
which will
remain true for
at
least one byte after the last CRC check
byte,
giving the processor time
to read the
flag.
The data, clock, and BDONE are supplied to the CRC device on
a
3-bit mini
bus.
During read operations, the
serial-to-parallel device
(U9)
will be sourcing these lines
since the WRITE control line from MAC CNTRL
(U29) is
low and
this
enables tri-state drivers on these
lines. The
40