Radio Shack TRS-80 Service Manual page 34

5-Meg Hard Disk Service Manual
separation. Here, some background information may be
helpful
s
In
order
to
provide maximum data recording density
and therefore maximum storage efficiency, data
is
recorded
on the
disk using
a
Modified Frequency
Modulation
(MFM)
technique. This technique requires
clock bits to be
recorded only when two successive data
bits are missing
in
the serial data stream. This
reduces the total number
of bits
required
to
record
a
given amount
of
information on the disk* This results
in an
effective doubling
of the
amount
of the
data
capacity, hence the term "double density*"
Because clock bits are not recorded with every data bit
cell,
circuitry
that can remain
in
sync with data during the
absence
of clock bits
is
required. Synchronous decoding of
MFM data streams requires the decoder
circuitry
to
synthesize clock bits when they are present. This
is
accomplished by using
a
phase-locked oscillator employing
an
error amplifier/filter
to
sync onto and hold
a
specific
phase relationship
at the data and clock bits
in
the data
stream. The synthesized clock called RCLK can then be used
to
separate data bits from clock bits and
to shift the
resultant serial data into registers
for
parallelization
into bytes
.
Incoming Data Selection
Serial data
is
input from up
to
four radially connected
drives via
a
quad RS-422 differential receiver
(U54).
The
receiver converts differential input data
to
TTL levels for
use by the controller. The data from the selected drive
is
then routed
to
gate
(U53).
At this point, data and clocks
are still combined and appear
as 50
nanoseconds
(nominal)
active high pulses spaced at intervals of one,
one and
a
half, or two times the
RCLK period. This data
is
presented
to the input
of
another AND/OR/INVERT gate
(U4)
which will
gate either MFM data or
a
reference clock into
the first
stage
of the
VCO error amplifier circuitry.
Reference Clock
The reference clock
is
derived from the write clock crystal
oscillator
(Ql, U10,
and associated circuitry). This
oscillator uses
a
fundamental cut crystal
to
oscillate
at
four times the RCLK frequency. The 4X output
is
then divided
by UlO to produce both
a
2X clock (2XDR*), which
is
used
as
a
reference, and
a
IX clock (WCLK)
which
is
used
to
produce
/p
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