Radio Shack TRS-80 Service Manual page 37

5-Meg Hard Disk
Service Manual
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The term "capture range" can be described
as
the frequency
range centered about the VCO free running frequency over
which the loop can acquire
lock with the incoming data
signal*
The free running frequency
of the VCO
is
always twice that
of the RCLK rate.
In fact, RCLK
is
produced by
the VCO
through
a
divide-by-two counter
(U14).
Power for the VCO's internal oscillator
as
well
as for the
error amplification filter
is
supplied from
a
78M05 +5
volt
regulator. This insures good noise separation for these
stages from the power supply.
Error Amplifier
Control
of the
VCO
is
accomplished
by the error amplifier,
filter, and Data Separator
chip. The error amplifier
is a
balanced current mirror whose output sources
or
sinks
current
to the filter stage. Whenever the VCO
is
running too
slow, the error amplifier receives pulses from data bits
before pulses from the VCO clock. This causes the error
amplifier
to produce pump-up pulses
to the filter. The
filter integrates these UP pulses and raises the overall
voltage
of the voltage control input
(TP8)
to the VCO. When
the VCO
is
running too
fast, the error amplifier produces
pump-down pulses
to the filter. There will always
be some
error present because without pulses
of UP
and DN the filter
would float causing the VCO
to
drift
off center frequency.
Phase Detector
The circuitry which feeds
the error amplifier
is
called the
phase detector. This consists
of
several
"D"
latches
(U20,
U21) and
a
delay line
(U31).
The function of this circuit
is
to provide time windows during which
the leading edges of
the incoming
MFM data can
be
compared
to the leading edges
of the VCO
clock. These windows are approximately
50
nanoseconds
in
length and are initiated by the leading edge
of any data bit
as it
enters the detector. The windows are
terminated by the same data
bit, edge delayed by
a
net of
50
nanoseconds
(60
nanoseconds
in the delay line minus
approximately
10
nanoseconds
in
propagation delays.) When
both the delayed data bit and the nearest VCO clock edge
arrive at the detector, the detector
is
reset until the next
data bit arrives on the MFM data stream. The delayed data
bit sets its half of the
detector latches
to
produce the VP
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