Radio Shack TRS-80 Service Manual page 46

5-Meg Hard Disk Service Manual
Dynamic bit shift occurs
as
the result of one bit on the
disk
(a
flux reversal) influencing an adjacent bit* The
effect
is to
shift the leading edge
of
both bits closer
together
or
further apart than recorded. The net result
is
that enough jitter
is
added to the
data recorded on the
inside tracks
to
make them harder
to
recover without error.
In
any event, there
is a
method called write precompensation
which can be
applied
to
reduce the effect of this shift on
the data.
Write Precompensation
is a
way
of
predicting which direction
a
particular bit will
be
shifted and intentionally writing
that bit out of position
in
the opposite direction
to the
expected shift. This
is
done by examining the next two data
bits, the last bits, and the present bits to be written and
producing three signals depending on what these bits
are.
The three signals are EARLY, LATE, and NOM. They are used
in
conjunction with
a
delay line to
cause the leading edge
of
a
data/clock bit
to be
written early, late, or on time. As
with MFMW, these signals are subject
to
decoding slivers and
must
be retimed by U16.
The processor can enable
or
disable the generation
of
these
signals by controlling the RWC (Reduce Write Current) line
from
U52.
When RWC
is
high,
precompensation
is in
effect.
When RWC
is
low, no
precompensation
is
generated and
the NOM
output
of the
device
is
held
true.
The delay line, U31, actually performs the
precompensation
with the help
of an AND-OR-INVERT gate
(U37).
The MFMW
pulses are applied to the input of the delay line
and,
depending on which
of the
three precompensation signals
is
present, the U37 selects
a
different
tap on the delay line.
Nominal data
is
actually tapped from the second
tap,
early
data from the first, and late data from the third. From
U37,
the MFMW data
is
sent to the input of
a
quad driver
(U35 or
U36)
where
it is
converted
to a
differential form and then
sent to the disk drive. The
AND-OR-INVERT gate
(U37)
has one
other function.
If
the controller
is
not writing, the WGI
(Write Gate Internal) signal will
be low.
This
is
inverted
by U19 and applied to the fourth section of U37. This
resulting high input effectively inhibits the gate from
accepting MFMW
data.
Host Interface
The interface bus to the controller
is
pin-for-pin
compatible with the standard Model
III I/O port. This
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