Radio Shack TRS-80 Service Manual page 38

5-Meg Hard Disk
Service Manual
pulses
.
The VCO clock edge
sets its half of the detector to
produce the DN pulse.
Window Extension
Once the VCO has been locked onto the phase of the incoming
data, the
actual separation of data and clocks can occur.
This
is
accomplished by using
a
technique called window
extension. This technique causes data bits to first have
their leading edges shifted into the center of the RCLK half
cycles then
to
have them latched
or
extended until the next
rising edge of the RCLK, The
shift
is
accomplished by
tapping the data
of the
Sample on
Phase Detector delay line
at the
60
nanosecond
tap,
and inverting the VCO clock to the
RCLK divider (U14). The
delayed data clocks
a
pair
of
latches
(U12
and U13). The "data" latch has its
"D"
input
and CLEAR connected
to
RCLK* and the "clock" latch has
its
"D"
input and CLEAR connected
to
RCLK*,
If
an
MFM data
bit enters the latches while RCLK
is
high, it
will
be
extended
as
a
data bit. If RCLK* is
high,
it
will
be
extended
as
a
clock bit.
Due to this extension technique,
bits can jitter
approximately one-fourth the RCLK
period
without being
lost.
The output of each latch
is
then further
extended by being fed directly into the second half
of
the
latches and clocked on alternate edges of RCLK,
The final
outputs of the data extension/separation stage are two
separate signals? one signal consists solely
of
NRZ
(non-return
to zero)
data and the other of NRZ
(non-return
to zero)
clocks. The NRZ data and clocks are finally
in a
form suitable for
processing by subsequent circuitry on the
Controller board.
Clock Detection
Due to the nature of MFM data encoding,
it is
impossible
to
know exactly
if
MFM bits are data or clocks. This
ambiguity
results
in
having
to
create circuitry
to
assume that bits on
RCLK* are actually data bits until the VCO is
locked on and
a
unique data/clock pattern
is
detected. This
is
accomplished by holding the VCO to
RCLK divider
(U14)
reset
until
it is
fairly certain that bits on the data stream are
actually clocks belonging
to
a
field of zero data.
Once this assessment has been made, the processor releases
the
AM detector
(Ull)
by
raising the SRCH signal. This
signal releases
a
latch
(Ull)
which will remove DHOLD from
the
RCLK divider
(Ull)
on the next rising edge of
a
MFM data
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