Radio Shack TRS-80 Service Manual page 41

5-Meg Hard Disk
Service Manual
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TRS-SO
®
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along with BDONE. These signals are active only when WRITE*
is
high which indicates
a
read mode
of
operation*
CRC Checking Circuit
Data recorded on magnetic media
is
prone to
several types of
errors which could render data unusable if
some form of
error detection were not employed. Therefore,
a
cyclic
redundancy check
(CRC)
is
performed on
all data transfers
from the disk. The CRC
is
an
error detection code consisting
of 16
additional bits which are appended
to
every
ID
field
and data field on the disk. These bits are produced by
dividing the data stream serially with
a
large polynomial
.
This division produces
a
unique 16-bit value
for
any
information passed through the CRC generator
.
As
data
is
being read from the
disk, the CRC
generator
(U6)
re-computes the original CRC
bits* The
value
in
the CRC
generator must always be
zero after the last two bytes
(which
contain the orginal recorded
CRC)
are read.
When this
happens, the data was correctly read and the controller will
not flag an error.
If,
however, the CRC generator
is
not
zeroed after
it
has
checked all bytes
of
the recorded data,
the
controller will flag the data as
erroneous and enter
into
a
re-try condition.
If
the controller cannot get
correct data after attempting
to
read
it 16
times, the read
will be aborted and the host informed that the data
in
the
buffer
is
questionable.
The Controller board uses the same device
to
generate and
check CRC's for data being written to or
read from the disk.
The polynomial used
is?
16 12
5
X +
X + X +
1
(commonly called the CRC-CCITT
polynomial)
The processor polls the condition of the
DRUN circuitry
during read operations. When DRUN is
true,
it
begins to
search for an address mark. Once the AM
is
located, the
processor will start to
read parallel data which has been
converted from NRZ data by the serial-to-parallel device.
The processor will terminate this activity when
it has
received the information
it is
looking
for or
if
an
error
is
detected.
While the processor
is
reading the parallel
data, the CRC
generator
is
reconstructing the CRC check value. The CRC
generator
is
initialized by
the processor setting CRCIZ* low
Radio
HaelC
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