Wincor Nixdorf D425-CPU User Manual page 58

38 Initializes different devices through DIM.
39
Init DMA-1 & DMA-2
3A
Init RTC date/time.
3B
Test for total memory installed in the system. Also, check for
F2 or ESC keys to limit memory test. Display total memory in the
system.
3C
Mid POST initialization of chipset registers
40
Detect different devices (parallel ports, serial ports, and
coprocessor in CPU, etc.) successfully installed to the
system and update the BDA, EBDA, etc..
52
Updates CMOS memory size from memory found in memory
test. Allocates memory for Extended BIOS Data Area from base
memory. Programming the memory hole or any kind of implemen-
tation that needs an adjustment in system RAM size if needed.
60
Initializes NUM-LOCK status and programs the KBD typematic
rate.
75 Initialize INT-13 and prepare for IPL detection.
78 Initialize IPL devices controlled by BIOS and option ROMs.
7C Generate and write contents of ESCD in NVRAM.
84 Log errors encountered during POST.
85 Display errors to the user and gets the user response for error.
87
Execute BIOS setup if needed / requested. Check boot password
if installed.
8C
Late POST initialization of chipset registers.
8D
Build ACPI tables.
8E
Program the peripheral parameters. Enable NMI.
90 Initialization of system management interrupt by invoking
all handlers.
A1
Clean-up work needed before booting to OS.
A2
Takes care of runtime image preparation for different BIOS
modules. Initializes the Microsoft IRQ Routing Table.
A4
Display boot option popup menu.
A7 Displays the system configuration screen if enabled. Initialize the
CPU before boot, which includes the programming of the MTRRs.
A9
Wait for user input at config display if needed.
AA
Uninstall POST INT1Ch vector and INT09h vector.
AB
Prepare BBS for INT19h boot. Init MP tables.
AC
End of POST initialization of chipset registers. De-initializes the
ADM module.
B1 Save system context for ACPI. Prepare CPU for OS boot including
final MTRR values.
C0
Early CPU init start disable Cache, init Local APIC.
C1
Set up boot strap processor for Information.
C2
Set up boot strap processor for POST.
C5
Enumerate and set up application processors.
C6 Re-enable cache for boot strap processor.
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