Philips DVDR980/001 Service Manual page 311

GENERAL DESCRIPTION (continued)
of the two signals results in a BYTE WRITE cycle. CASL#
transitioning LOW selects an access cycle for the lower
byte (DQ0-DQ7), and CASH# transitioning LOW se-
lects an access cycle for the upper byte (DQ8-DQ15).
Each bit is uniquely addressed through the 20 ad-
dress bits during READ or WRITE cycles. These are
entered 10 bits (A0-A9) at a time. RAS# is used to latch
the first 10 bits and CAS#, the latter 10 bits. The CAS#
function also determines whether the cycle will be a
refresh cycle (RAS# ONLY) or an active cycle (READ,
WRITE or READ-WRITE) once RAS# goes LOW.
The CASL# and CASH# inputs internally generate a
CAS# signal that functions like the single CAS# input
on other DRAMs. The key difference is each CAS# input
(CASL# and CASH#) controls its corresponding eight
DQ inputs during WRITE accesses. CASL# controls
DQ0-DQ7, and CASH# controls DQ8-DQ15. The two
CAS# controls give the 1 Meg x 16 both BYTE READ and
BYTE WRITE cycle capabilities.
V
IH
RAS#
V
IL
CASL#/CASH# V
IH
V
IL
V
IH
ADDR ROW
V
IL
V
IOH
DQ
V OPEN
IOL
V
IH
OE#
V
IL
Circuit-, IC Descriptions and List of Abbreviations
COLUMN (A)
VALID DATA (A) VALID DATA (A)
t OD
t OES
t OE
The DQs go back to
t
Low-Z if OES is met.
Figure 1
OE# Control of DQs
A logic HIGH on WE# dictates read mode, while a
logic LOW on WE# dictates write mode. During a WRITE
cycle, data-in (D) is latched by the falling edge of WE or
CAS# (CASL# or CASH#), whichever occurs last. An
EARLY WRITE occurs when WE is taken LOW prior to
either CAS# falling. A LATE WRITE or READ-MODIFY-
WRITE occurs when WE falls after CAS# (CASL# or
CASH#) was taken LOW. During EARLY WRITE cycles,
the data outputs (Q) will remain High-Z, regardless of
the state of OE#. During LATE WRITE or READ-
MODIFY-WRITE cycles, OE# must be taken HIGH to
disable the data outputs prior to applying input data.
If a LATE WRITE or READ-MODIFY-WRITE is attempted
while keeping OE# LOW, no WRITE will occur, and the
data outputs will drive read data from the accessed
location.
The 16 data inputs and 16 data outputs are routed
through 16 pins using common I/O. Pin direction is
controlled by OE# and WE#.
The 1 Meg x 16 DRAM must be refreshed periodi-
cally in order to retain stored data.
COLUMN (B) COLUMN (C)
VALID DATA (B)
t OD
t OEHC
The DQs remain High-Z
until the next CAS# cycle
t
if OEHC is met.
DVDR980-985 /0X1
COLUMN (D)
VALID DATA (C)
t OD
t OEP
The DQs remain High-Z
until the next CAS# cycle
t
if OEP is met.
9. EN 311
VALID DATA (D)
DON'T CARE
UNDEFINED