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EN 228
9.
DVDR980-985 /0X1
STi5508
1
Architecture overview
1.1
Introduction
The figure below shows the architecture of the STi5508. This device has the same global architecture as the STi5505,
with the addition of new features such as karaoke, a shared SDRAM memory interface and extra display planes.
Because of this increased performance, the STi5508 and STi5505 are not pin compatible. This chapter gives a brief
overview of each of the functional blocks of the STi5508.
2 UART &
2 SmartCards
Internal peripherals
I2C
Front-end &
link interface
DVD
Programmable
Ext peripherals:
CPU interface
(EMI)
Flash, additional
DRAM SDRAM
Shared SDRAM
16, 32 or
interface (SMI)
64 Mbit
SDRAM
Analog/digital
video output
Circuit-, IC Descriptions and List of Abbreviations
Central
command port
DMAs
DMA
Communications
arbiter
ST20 arbiter & memory controller
SDRAM
I/F
BLOCK MOVE
SDRAM arbiter (LMC)
OSD, SP
Video
DENC
decoder
filtering
and mixing
Figure 1 Functional block diagram
CPU
CACHE SUBSYSTEM
(C2+)
RID
CLOCK
GENERATION
Refill
control
CPU arbiter
CD FIFOs
Command I/F
Audio
Video
Karaoke
decoder
decoder
processor
1 Architecture overview
TAP
ICACHE
SRAM
DCACHE
Diagnostic
JTAG
controller
debugging
interface
Audio in/out
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