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Philips DVDR985
Technical Training Manual
Philips Service and Quality/Training
One Philips Drive
Knoxville, TN 37914-1810
P. O. Box 14810
PH: 865-521-4397
FAX: 865-521-4818
EMAIL: TECHNICAL.TRAINING@PHILIPS.COM

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   Summary of Contents for Philips DVDR985

  • Page 1 Philips DVDR985 Technical Training Manual Philips Service and Quality/Training One Philips Drive Knoxville, TN 37914-1810 P. O. Box 14810 PH: 865-521-4397 FAX: 865-521-4818 EMAIL: TECHNICAL.TRAINING@PHILIPS.COM...
  • Page 2 Troubleshooting Section. closely that of DVD ROM. See Figure 1. It also uses Direct Overwrite when a RW disc is used. The DVDR985 is the forth in a line of DVD recorders. The DVDR1500 was the first. Laser Technology...
  • Page 3 Figure 2 – CD Laser Operation light reflecting from the disc. The pulses are created by Pits in the Reflective Layer of the disc. The Pits reflect less light than the intact surface of the Reflective Layer, called Lands. Disc Mechanical Layout The DVD and CD share much of their tech- nology.
  • Page 4 Figure 4 - The Disc As shown in Figure 4, the CD is subdivided into The production of a disc is a high tech process three parts: the Lead In Track, the Program explained in Figure 5. The process starts with Area, and the Lead Out Area.
  • Page 5 Frequency information, HF, is demodulated and A partially recorded disc’s Information Area has stored in RAM. When the RAM is half full, the four sections: a PCA/RMA area, a Lead In Area, data is fed out to the Digital to Analog a Recorded Program Area, and a Recordable Converters.
  • Page 6 during recording. The dye based RW recordable Re-Recording Process layer provides a reflectivity of 40% light return The Re-Record process shares much of its oper- and 70% light return. 40 percent reflectivity rep- ation with that of a CDR. The blank disc’s resents Pits and the 70% represent the Lands.
  • Page 7 DVDs measuring 22.7 mm centered to 24 mm cen- All of the previously discussed technologies tered. The Information Area is limited to 116mm apply to the DVD. Like CDs, DVDs are also centered. stamped into play only discs. In this discussion, we will point out the differences between DVDs Two of the big differences between DVDs and and CDs.
  • Page 8 Figure 10 - Wobble Pregroove Wobble Dual Layer Discs Two information layers are separated by a thin A Pre-groove is stamped on writable discs. transparent layer. Refer to Figure 11. The first All recordable DVD media types feature a micro- layer is partially transparent.
  • Page 9 Figure 12 – PTP and OTP Layout This allows instant access to the additional data Capacity or scene. OTP is Opposite Track Path. This Because a stamped DVD can be Dual Layered method links the end of one layer to the begin- and Double Sided, there are four different capac- ning of the other.
  • Page 10 Automatic Self Diagnostic Modes (End User/Dealer Script Interface) Description VideoEncI2c The End User/Dealer Self Diagnostics work with- Checks the interface between the host I2C con- out the need for other equipment. A number of troller and Empress hardware tests are automatically executed to check for faults in the recorder.
  • Page 11 Color bars appears on the output. It is a PAL col- Clock11.289MHz orbar pattern which means you may see a Switches the A_CLK of the micro clock to greyscale bar pattern. The pull in range of the 11.2896 MHz monitor, will affect what is seen. An NTSC color bar signal can be output from the Host Decoder using ComPair.
  • Page 12 Manual Service Diagnostics (Player Script) Description The display shows FP SEGM. Press PLAY to start the test. First the starburst pattern is lit, The Manual Diagnostics provide the opportunity then the horizontal segments are lit, followed by to perform tests and exercise the unit in a way the vertical segments and the last test lights all that helps determine which of the DVD the segments.
  • Page 13 The display shows FPDIMMER. Press PLAY to The display shows BE TRAY CLOS. This closes activate the dimming feature. Press Play to con- the tray. firm that the text on the local display was dimmed. The display shows ERRORLOG READ. If there was an error a code will be displayed.
  • Page 14 fails. 11707 - Setup of Front panel failed 10503 11708 - Sine on Front panel keyboard failed HostDec SDRAM Physical memory device test fails. 11801 - Init of I2C failed 10601 - HostDec DRAM Memory data bus test 11802 - The muting of the Audio failed fails.
  • Page 15 13101 - Can not find version in FLASH. 20306 - Error audio encoder SRAM access stuck-at-zero data line 13200 - Diagnostics application version: diagver- sion 20307 - Error audio encoder SRAM access stuck-at-one data line 13201 - Can not find version in FLASH. 20308 - Error audio encoder SRAM access 13300 - Download application version: download stuck-at-one address line...
  • Page 16 load boot 20704 - Error audio encoder I2C bus busy 20504 - Error audio encoder cannot download test code 20705 - Error audio encoder I2C cannot write slave address 20505 - Error audio encoder SRAM WRR cannot obtain result of test 20706 - Error audio encoder I2C no acknowl- edgement received 20506 - Error audio encoder WRR SRAM stuck-...
  • Page 17 30006 - VSM SDRAM Bank2 Physical memory 30303 - Interrupt A wasn’t raised. device test fails. 30304 - Interrupt B wasn’t raised. 30007 - VSM SDRAM Bank1 VSM interrupt reg- ister A has a-stuck at- error for value: 30305 - Interrupts A and B were raised. 30008 - VSM SDRAM Bank2 VSM interrupt reg- 30401 - VSM SDRAM Bank1 Memory data bus ister A has a-stuck at- error for value:...
  • Page 18 40402 - NVRAM error log is invalid 50210 - The front panel did not show vertical segments. 40403 - Front panel failed 50304 - Execution of the command on the 40701 - NVRAM error log reset; I2C failed Analog Board failed. 40900 - Region code Change counter is reset 50305 - The front panel could not be accessed by the Analog Board.
  • Page 19 50605 - Front panel remote control; no user by the Analog Board. input received 51403 - The beeper did not sound. 50701 - Execution of the command on the Analog Board failed. 51404 - The user skipped the FP-Beep test. 50702 - The front panel could not be accessed 51405 - The user returned an unknown confirma- by the Analog Board.
  • Page 20 60101 - Basic Engine returned error number 0x 51802 - The front panel could not be accessed error number by the Analog Board. 60102 - Parity error from Basic Engine to Serial 51803 - The front panel could not be dimmed. 60103 - Communication time-out error 51804 - The user skipped the FP-Dim test.
  • Page 21 60504 - Unexpected response from Basic Engine 61503 - Communication time-out error 60601 - Basic Engine returned error number 61504 - Unexpected response from Basic 0xerrornumber Engine 60602 - Parity error from Basic Engine to Serial 61601 - Basic Engine returned error number 0xerrornumber 60603 - Communication time-out error 61602 - Parity error from Basic Engine to Serial...
  • Page 22 61718 - BE VSM Sector processor initialization 0xerrornumber failed 62102 - Parity error from Basic Engine to Serial 61719 - BE VSM sector processor DMA initial- ization failed 62103 - Communication time-out error 61720 - BE VSM sector processor DMA start 62104 - Unexpected response from Basic failed Engine...
  • Page 23 0xerrornumber 63101 - Basic Engine returned error number 0xerrornumber 62702 - Parity error from Basic Engine to Serial 63102 - Parity error from Basic Engine to Serial 62703 - Communication time-out error 63103 - Communication time-out error 62704 - Unexpected response from Basic Engine 63104 - Unexpected response from Basic Engine...
  • Page 24 63502 - Parity error from Basic Engine to Serial 64108 - The VSM BE out initialization failed 63503 - Communication time-out error 64109 - The VSM BE out DMA start failed 63504 - Unexpected response from Basic 64110 - The VSM BE out start failed Engine 64111 - The rec command failed 63505 - Error string Ö...
  • Page 25 64129 - The calibrate-record command failed Board. 64130 - To many retries 70602 - Communication with Analog Board fails 64131 - BE update RAI command after writing 70700 - Frequency download OK failed 70701 - Wrong frequency table size. 64132 - BE find first recordable address com- mand failed 70702 - Can not download the frequency table into the Analog NVRAM.
  • Page 26 72103 - Invalid input. 71203 - Communication with Analog Board fails 72104 - Communication with Analog Board fails 71300 - Audio routing on the Analog Board OK 72201 - Initializing the 1Hz signal on the Clock 71301 - Routing the Audio on the Analog Board IC failed fails.
  • Page 27 73202 - Invalid input. 80211 - We tried to receive a reply for 73203 - Communication with Analog Board fails DVIO_MAX_RETRIES_ACKREPLY times !! 80000 - The DVIO module is present in the sys- 80212 - We tried to receive a reply for tem.
  • Page 28 80309 - Maximal number of retries reached by 80408 - Software Error in function Handle State Handle State Sending!! Awaiting Reply!! 80310 - Maximal number of retries (NACKs) 80409 - Maximal number of retries reached by reached (Handle State Sending) Handle State Sending!! 80311 - We tried to receive a reply for 80410 - Maximal number of retries (NACKs)
  • Page 29 80508 - Software Error in Handle State Awaiting Reply function! 80605 - Unable to send the configuration to the DVIO module. 80509 - Maximal number of retries reached by Handle State Sending! 80606 - Unable to download the chip ID to the DVIO module.
  • Page 30 80702 - The I2C could not be initialized. tics mode failed 80703 - The DVIO module could not be reset. 90121 - Error: Audio data in host memory con- tains wrong frequency: frequency Hz 80704 - Unable to receive the reset indication from the DVIO module.
  • Page 31 input 90301 - Initialization of I2C failed 90212 - Cannot Initialize VSM AV-out DMA port 90302 - I2C communication to VIP failed 90213 - Cannot Initialize VSM AV-out port 90303 - Initialization of VIP failed 90214 - Cannot start VSM AV-out DMA port 90304 - Generation of Close Caption data failed 90215 - Cannot start VSM AV-out port 90305 - VIP not locked to Video signal...
  • Page 32 90415 - Cannot start VSM AV-out port 90505 - VIP not locked to Video signal 90416 - Transfer of data from VSM to host decoder failed. 90506 - Initialization of VBI Extractor failed 90417 - VSM and Hostdec memory do not match 90507 - No CC data received (compared after transfer) 90508 - Closed Caption data overrun...
  • Page 33 decoder failed. 90707 - No CC data received 90617 - VSM and Hostdec memory do not match (compared after transfer) 90708 - Closed Caption data overrun 90618 - Decoding of the Video data in the host 90709 - Closed Caption data does not match decoder memory failed 90710 - Switch off colorbar failed 90619 - The data in the host decoder is not...
  • Page 34 90817 - Error cannot start VSM AV out DMA port 90908 - Error cannot initialize VSM audio in port 90818 - Error cannot start VSM AV out port 90909 - Error cannot initialize VSM audio in DMA port 90819 - Error transfer data from VSM to host decoder 90910 - Error cannot initialize VSM audio out DMA port...
  • Page 35 rate read failed 90927 - The CRC of the audio frame is wrong 141225 - Progressive Scan Board I2C AD7196 write access time-out 90928 - The audio frame is not MPEG-I layer II ! 141226 - Progressive Scan Board I2C AD7196 90929 - Error cannot de-mute DAC on Analog no write acknowledgement Board...
  • Page 39: Overall Block

    Overall Block Digital PCB This module performs many functions. It inter- Key Components faces between the Basic Engine and the rest of the unit. The unit is made up of: the Power Supply, the Front Panel, the Basic Engine, the Digital Board, During record, it encodes analog video into a the Analog Board, and the Digital Input/Output recordable digital data stream.
  • Page 41: Power Supply

    Power Supply components and large enough to turn On 7140, 7125 is turned Off by 7140. Diodes 6130, 6131 and 6132 protect the control circuit in case of This unit uses a stand alone Switch Mode Power failure of the MOSFET by providing an upperlimit Supply, SMPS.
  • Page 42: Front Panel

    Overcurrent Protection Circuit Fluorescent Display driver This circuit consists of R3145, C2143, a thyristor circuit formed by T7141 and T7143, R3143 and Monitoring the keyboard matrix R3142. When the output is shortened, the cur- rent through the FET will produce a large voltage Decoding the remote control commands drop across the source resistors of the FET.
  • Page 43 Figure 18 - Front...
  • Page 44 Panel Circuit...
  • Page 45 IR Receiver The IR receiver, 7140, contains a bandpass amplifier as well as a photo-diode. Refer to Figure 19. The photo-diode receives approxi- mately 940nm infrared pulses. The pulses are amplified and demodulated. On the output of the IR receiver, 7140, is a pulse sequence at TTL levels.
  • Page 46 Basic Engine Block Diagram DVD Mechanism and Servo Some specifications: Board Record DVD+R and R/W Lossless linking Basic Engine Recording speed: 1.2 x Playback DVD, DVD+R(W), DVD (SL/DL), The Basic Engine consists of a DVD-Mechanism DVD-R, DVD-RW (V1.1) with dual laser Optical Pickup Unit (OPU), a tray Playback speed: 1.2 x loader, a fan unit, and a PCB containing all elec- Playback CD, CD-DA, CD-R, CD-RW, CD-...
  • Page 47 Figure 21 - DVDR Mechanism DVDR Mechanism The SPIDRE is the Signal Processor IC for DVD Recordable The MACE3 is the Mini All in one CD Engine The DVDR-M is made up of three components: third generation. Optical Pickup Unit, OPU, the Sled, and the The Encoder/Decoder is the Translation cir- Turntable Motor.
  • Page 48 DROPPI The DROPPI (DVD Rewritable OPU Pre- Processor IC) is a multi-purpose analog pre- processor. It supports many photo detector con- figurations and output signal modes. It produces RF and servo feedback signals, Q1-Q6. Its out- put signals are on the same flex ribbon cable with the wideband RF (differential signals).
  • Page 49 Figure 23 - Laser Drive IC...
  • Page 50 LADIC of the Optimal Laser Current is preformed. The disc is written to again except the current range The Laser Drive IC, LADIC, controls the data to is chosen by the MACE3 using the feedback the lasers, and the supply to them. It performs received.
  • Page 51 Figure 24 - Servo Block Diagram Servo Circuit Description SPIDRE The SPIDRE (Signal Processing IC for DVD The Servo circuit provides the interface between REwritable) is a multi-purpose analog pre- the Mechanism and The Digital Signal processor IC specifically intended for writing Processing Board.
  • Page 52 and tilt sensor signal. The HF/RF (EMF) signal varies greatly between disc formats. The Focus Error and Radial Error signals come from the mechanism on the Q1-6 signal paths. The Tilt Error has a Photo Tilt Sensor. The dynamic range of these signals is very large. They are converted to Lower frequency RF data paths that the MACE3 can accommodate.
  • Page 53 igure 25 - PRE- Processor...
  • Page 54 Figure 26 - PCS Motor MACE3 Servo Microcomputer generates the control signals for tray control. In a CD/DVD system, there are several active control loops. Some of them are needed to adjust the The MACE3 IC is the Mini All Cd Engine third servo error signals.
  • Page 55 axial (focus), and tangential directions (Tilt). This The MACE3 uses a Parallel communication bus access system consists of two parts, namely the for access to its Flash ROM. Refer to Figure 29. Focus Actuator and the Sled, which are, within a The Flash Memory contains the firmware for the certain range, mechanically and electrically inde- BE.
  • Page 56 Figure 29 - MACE3 Circuit...
  • Page 58 Figure 30 - Wobble Tracks Wobble wobble frequency (817kHz), which ensures that the writing can be started and stopped at an A Pre-groove is stamped on writable discs. All accurately defined position. The writing clock as recordable DVD media types feature a micro- obtained from this groove is very accurate.
  • Page 59 Encoder/Decoder/HDR65 The spindle-motor interface provides both motor control signals from the demodulator and, in addition, contains a tachometer loop that accepts The Encoder/Decoder has the following func- tachometer pulses from the motor unit. The tions: motor is a standard three phase motor. Motor speed is controlled by the Wobble Processor ·...
  • Page 60 Figure 31 - Encoder/Decoder...
  • Page 62 Motor Drivers are amplified and provided to the motor on Pins 12-5 of IC7306. The motor drivers each receive an error or con- Sled Motor Driver trol voltage. There are 6 motor drivers in this THe MACE3 produces the SL control voltage for unit: the Focus Motor Driver, the Radial Motor the driver circuit.
  • Page 63 Figure 32 - Motor Drivers...
  • Page 65 Figure 33 - Digital Processor Block...
  • Page 67 Digital Signal Processor EMI Bus The VSM and the MPEG2 Decoder share a Data Bus called the External Memory Interface, EMI. The EMI contains 4 Megabytes of Flash The Digital Signal Processor has many responsi- EEPROM. The EEPROM contains the Firmware bilities.
  • Page 68 Figure 34 - Power Clock and Reset of the Digital Signal Processor System Clocks clock and Word clock, AE_BCLK and AE_WCLK. They are sent to the VSM. The System Clocks (27MHz) of the VSM, On/Off EMPRESS, and Progressive Scan circuits are generated by an oscillator, 7906.
  • Page 71 Video Input Processor Record Mode Analog Video input signals CVBS, YC, and YUV are routed via the Analog Board to connector 1601 on Pins 14, 16, 18, 20, and 22. The signals are sent to IC7500, the Video Input Processor, VIP.
  • Page 73 Versital Stream Manager The VSM is a buffer and a gateway for the data streams going to and from the Basic Engine, BE, and the rest of the data Processors. It selects which video source is to be sent to the BE for recording.
  • Page 75 EMPRESS The EMPRESS IC encodes the Digital Video stream into an MPEG2 Video stream that is fed to the VSM. Refer to Figure 38. I 2 S Audio is sent from the Analog Board to IC7403/EMPRESS via connector 1602. The EMPRESS compresses I 2 S Audio data into an AC3 Audio stream that is fed to IC7100 (VSM).
  • Page 77 MPEG2 Decoder Power On IC7200 participates in the initilazation of the unit. Playback Power up occurs in two stages. 7200 participates During playback, the serial data from the Basic in the second stage. After the Analog board and Engine goes directly to the MPEG2/AC3 the Front Panel Microcomputer check the unit Decoder, IC7200 via the serial Front End I 2 S and pass their tests, the Analog Microcomputer...
  • Page 79: Progressive Scan

    Progressive Scan The progressive scan section is integrated into the Digital Board and built around the SAGE Fli2200 Deinterlacer/Line Doubler (7700). Refer to Figure 40. This I 2 C controlled device uses 64Mbit SDRAM (32bit x 2M) to perform high quality de-interlacing (meshing).
  • Page 81 D/A Converter The output of 7701 (4:4:4 progressive Video) is fed to the Analog Device, 7801. The RGB output is a current signal fed via a low pass filter to the output Op Amps, 7802 and 7803. The Analog Video, 480P, is fed via a 7 poled flex to the Analog Board.
  • Page 84 Figure 43 - Analog Board Power circuit Analog Processor Board ISTBY line goes Low, 7329 turns Off. R3336 turns On 7324. This switches 7321 and 7323 The Analog Board controls all analog input/out- put selection, and routing. It houses the System There is also a power fail circuit, which is neces- Control Microcomputer.
  • Page 85 Power up Microcomputer allows 10 seconds for the UART1 response. If it does not come, the unit goes into 7803 controls power up of the unit. There are sleep mode, and will not accept keyboard input. three layers to the power up sequence. The first layer involves the Analog Board and the Front When the Front Panel Microcomputer receives a Panel.
  • Page 87 Power Switching The 3.3Vdc and the 5Vdc supplies are switched by the System Control Microcomputer. Refer to Figure 44. The 5Vdc Standby and the unswitched 3.9Vdc are sup- plied to two FETs, 7501 and 7520. 7515, 7511 and 7512 control 7501 and 7520. The -5Vdc Standby, the 33Vdc control voltage, and the 12Vdc regulated supplies are continuously pre- sent on 7515 and 7511.
  • Page 89 Tuner 1705 The Tuner is capable of receiving 125 channels, and is cable ready. Refer to Figure 45. The RF connections on the back of the unit provide an RF loop through. There is no RF Modulator, as seen in VCRs. The Tuner/Demodulator receives two supply voltages, 33Vdc and SW5Vdc.
  • Page 91 Audio Demodulator The Sound Processor, 7600, demodulates the Audio and performs A/D and D/A conversion. Refer to Figure 46. The I 2 C bus controls its operation. It uses two power supplies, the 5Vdc and the 8V Switched. IC 7600 has its own oscil- lator on Pins 5 and 6.
  • Page 93 Video and Audio Routing and 56. Digital Board input and Tuner Audio is routed via 7600 to 7507, Pins 39 and 41. 7507 The A/V I/O switching is controlled by a switch- selects the audio source. ing matrix, 7507. Refer to Figure 47. It is con- trolled via the I 2 C Bus.
  • Page 94 Figure 49 - Rear Input Selection There are also two SVideo input connection pos- The Audio I/O switching is also controlled by sibilities: Front and Rear SVideo In, which are 7507 via the I 2 C Bus. Analog Audio coming from connected to the input selector IC 7400 and Rear External Inputs 1,2 and External 3 are 7401.
  • Page 95 Figure 50 - Rear Output Jacks Output Jacks CVBS Out is provided by the 75 Ohm driver 7430. Both CVBS output sockets are connected to 7430 in parallel. Independent of which input signal is being used: CVBS, S-Video, or Y/UV, 7507 supplies SVideo and Y/UV signals to the corresponding sockets.
  • Page 96 Figure 51 - RGB-Y/UV Conversion The Y/UV In signal is routed directly to the Digital Board; there is no Y/UV IN to Y/UV Out This is accomplished by 7004, Refer to Figure loop through in Standby. Refer to Figure 51. The 52.
  • Page 98 Figure 53 - Digital Input and Output Jacks on the Analog Board Digital Output The unit provides two Digital Audio output con- nections. One uses a coax output connector, and the other uses a fiberoptic connection. The Digital Audio output signal is gated by 7470 and transformer coupled to connector 1945.
  • Page 99 Figure 54 - Fan Control Circuit Fan Control age is approximately. 5V and will reach approxi- mately 10V at a temperature of 40°C. The The Fan Control circuit is necessary to control Microcomputer controls the On/Off function of the speed of the cabinet fan, 1984, and the BE the two fans via control line ION_FAN and Fan according to the changes of temperature SW_BE_FAN.
  • Page 101 Digital Video Input Board DV Decoder The AV data goes from the FIFO to the NW700. The DVIO Module is a decoder for DV streams. It decodes the stream into video data in 656 for- DV from a camcorder, IEEE1394, input stream mat.
  • Page 106: Troubleshooting

    TroubleShooting reset signals for: the DIVIO Board, two of them The Power Supply go to the EMPRESS and one to the BE. The Host Decoder expects a response on the I 2 C This Power Supply operates whenever AC power Bus from: the EMPRESS, the VIP, and both is applied.
  • Page 107 Check the voltage on the source. It should be a ply is asking for more output, and the problem is few tenths at most. If it is higher, check the on the primary side. source resistors and the FET. It is a good idea anytime the FET is replaced to replace the If the diode portion has a volt or more on it, the source resistors.
  • Page 108 The Front Panel/ Display Board on the Front Panel, the microcomputer on the Analog Board, and two microcomputers on the Digital Board. If the display is working, the Front Problems on the Front Panel display fall into four Panel should be showing four dashes. This categories: no display function, improper display means the Power up Reset and self check has function, no keyboard function, and no remote...
  • Page 109 The Digital Board cuitry is in operation as well. The output of the VSM supplying the BE is in the middle of the cir- cuitry on the Digital Board. Check the Digital The Digital Board is central to the recorder’s Video stream here.
  • Page 110 lator. The RF signal merely loops through. Tuner No power up involves the MACE3 operation needs to be checked on the Video Microcomputer. It is the System Control for the Outputs. BE. Like any microcomputer, first check the sup- plies, the Oscillator, and the Reset to the IC. No Tuner Functions Then check for the SUR line.
  • Page 111 List of Abbreviations +12V +12V Power Supply +2V5_FLI +2V5 Power Supply for FLI +2V5_PLL +2V5 Power Supply for PLL +3V3 +3V3 Power Supply +3V3_ANA +3V3 Power Supply Analog +3V3_DD +3V3 Power Supply Digital +3V3_DLY +3V3 Power Supply for IC7500 +3V3_DV +3V3 Power Supply for IC7404 +3V3_FLI +3V3 Power Supply for FLI...
  • Page 112 AE_DATAO Audio Encoder Output Data (PCM) Audio Encoder I 2 S word Clock AE_WCLK Audio Encoder I 2 S word Clock to DVIO AE_WCLK_DV Audio Encoder I 2 S word Clock to VSM AE_WCLK_VSM ANA_WE Analog write Enable Decoder ANA_WE_LV Analog write Enable Low Voltage AUD_BCLK Audio Bit Clock...
  • Page 113 CLK27M 27MHz Clock CLK27M_CON 27MHz Clock to Digital Board CLK27M_DV 27MHz Clock Digital Video Codec CLK27M_OSC\ 27MHz Clock IC7304 CLOCKGENAUD Clock generator Audio CLOCKGENVID Clock generator Video Constant Linear Velocity ComPair Computer aided rePair Cosphi Cosine Position of Hall info CPUINT0 Control processor unit interrupt CPUINT1...
  • Page 114 DV_HS_IN DVCODEC Horizontal synchronization In DV_HS_OUT DVCODEC Horizontal synchronization Out DV_IN_CLK Digital Video in Clock from DVIO Board DV_IN_DATA (7:0) Digital Video in Data bus from DVIO Board DV_IN_HS Digital Video in horizontal synchronization from DVIO Board DV_IN_VS Digital Video in vertical synchronization from DVIO Board DV_LCN DVCODEC Last Code Interrupt DV_PDN...
  • Page 115 I 2 S Integrated IC Sound Buss (3.3V High) INITN Initiate Configuration IO (0:30) Data bus of IC7404 Inverted ON: Enable the power Supply for the Digital Board when LOW IRESET_DIG Initialization of the Digital Board, HIGH when power ON ISPN In System Program Line (used for programming IC7203) JTAG3_TCK...
  • Page 116 SM_WEN SRAM write Enable SMA (17:0) SRAM Address Output SMD (15:0) SRAM Data Input/Output SPDIF Sony Philips Digital Interface for Audio SPIDRE Signal Processing IC for DVD REwritable SRAM Static Random Access Memory SRAMCE0N SRAM processor chip Enable 0 SRAMRDN...
  • Page 117 SVCD Super Video CD Subcode Tacking information/Track number/and disc location information SYSCLK_EMPRESS System Clock EMPRESS SYSCLK_PROGSCAN System Clock Progressive Scan Boundary scan Test Clock Boundary scan Test Data Input Boundary scan Test Data Output TDO_CONF Boundary scan Test Data Output from IC 7309 Track Loss signal Boundary scan Test Mode Select Track Position Indicator...
  • Page 118 VIP_HS Video Input Processor horizontal synchronization VIP_ICLK Video Input Processor Input Clock VIP_IDQ Video Input Processor Output Data qualifier VIP_IGP1 Video Input Processor Input general purpose 1 VIP_INT Video Input Processor interrupt VIP_RTS1 Video Input Processor ready to send VIP_VS Video Input Processor vertical synchronization VIP_YUV (7:0) Video Input Processor Digital Video (CCIR 656)
  • Page 119 Written by Dan Crum Version 6.5...

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