Table of Contents
Advertisement
EN 162
9.
DVDR980-985 /0X1
9.2.4
Motor Driver Flap
The flap-motor is controlled via the 2 Port-Pins (MD1, MD2) of
the P (7156, Pin 12, Pin 100). The motor driver part is
constructed as a bridged dual power operational amplifier.
Between the IC outputs (7120, Pin1, Pin3) and a Boucherot
circuit (2121, 3126) suppresses a spurious 3MHz oscillation
from the output stage. The two ports-pins (MD1, MD2) of the P
are PWM-outputs and are controlled in the following way:
Flap Motor:
MD1
off
H
open
H
close
L
Duty Cycle 50% for OPEN and CLOSE
Duty Cycle app. 10% for CLOSE
Duty Cycle app. 10% for OPEN
Figure 9-3
For the detection of the end-positions of the flap there are two
switches (1178, 1179) installed and the information is
evaluated from the P via the signals SW_1178 and SW_1179.
Flap Switches:
SW1
open
L
closed
H
moving
H
error
L
9.2.5
Bi-Color LED (Standby and ON)
The STBY-LED is a red/green bi-color-LED and is controlled
via the STBYLED-signal of the P (7156 Pin 10) in the following
way:
Colour of STBY
LED
red
green
9.3
Analogue Board Europe
9.3.1
Microprocessor TMP93C071F
The microcontroller „AIO" TMP93C071F is a 16bit
microcontroller with internal ROM and 8kB RAM. It includes the
following functions:
Circuit-, IC Descriptions and List of Abbreviations
MD2
L
PWM(H)
PWM(L)
CL 16532095_112.eps
150801
SW2
H
L
H
L
Status of the Set
STBY
ON
•
A/D converters
•
composite sync input
2
•
I
C bus interface
Following connection to the mains, a positive pulse on the reset
input on the P is generated by the reset-IC TL7705 (Pos.7900).
The system clock is generated with the 20MHz quartz (Pos.
1994).
9.3.2
Bus Systems
The communication between the P and the other functional
2
groups is via the I
C-bus (SDA, SCL). The clock rate is approx.
95kHz.
Functional groups on the I
2
•
E
PROM ST24E16 (Pos. 7815)
•
Tuner (Pos. 1705)
•
Matrix-switch STV6410 (Pos. 7507)
•
Audio IC / MSP (Pos. 7600)
•
Display board (Pos. 1987)
•
VPS-IC (Pos. 7990).
2
9.3.3
E
PROM
2
The E
PROM ST24E16 (Pos. 7815) is an electric erasable and
programmable, non-volatile memory. The E
specific to the device, such as the AFC-reference value, clock-
correction-factor, etc. The data is accessed by the P via the
2
I
C-bus.
9.3.4
VPS, PDC, Teletext (Europe Only)
The STV5348 (Pos. 7990) is a VPS, PDC, and Teletext
Decoder with an external 13,875Mhz quartz.
The following data formats are identified:
•
VPS (Timer data and station name)
•
PDC Format 2 (Timer data and station name)
•
PDC Format 1 (station name and time)
•
TXT header line (time for „time download")
9.3.5
FOME
The FOME-circuit compares the video signal coming from the
tuner and the one coming from the Scart-plug 1. If the video-
signals are identical the output of the FOME-circuit is low.
9.3.6
Fan Control
The fan control circuit is necessary to control the speed of the
cabinet fan (Pos. 1984) according to the requirements in
temperature and noise. The temperature is measured via an
NTC on the display board (Pos. 3145). When the temperature
is lower than 25° C the fan-voltage is approx. 5V and will reach
approx. 10V at a temperature of 40° C. It is also possible to
switch off the fan via the control line ION_FAN. The circuit
generates also two control-signals: TEMP goes to the P and
BE_FAN is the control-line for the basic engine fan.
9.3.7
Power Supply
The 5SW and 8SW supply are switched off in case of standby
from the P via the ISTBY-line. This is possible for power-save.
The ISTBY-line must be low in case of STBY. There is also a
„power fail" circuit on the PS-schematic which is necessary to
mute AUDIO when IPFAIL is low.
9.3.8
Front End (TU, AP Part)
The Front End Comprises the Following Parts:
•
Tuner [1705]
•
IF amplifier & video demodulator IC TDA 9818 [7703]
•
Sound processor MSP3415G [7600]
2
C bus:
2
PROM stores data
Advertisement
Table of Contents
