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9.5
Digital Board
9.5.1
Record Mode
Video Part
Analog Video input signals CVBS, YC and UV(RGB for EURO
and YUV for USA) are routed via the analog board to connector
1601 and sent to IC7500 SAA7118 (Video Input Processor).
Digital video input signals (DV_IN_DATA(7:0)) are sent from
the DIVIO board through the connector 1603 and further also
to IC7500.
IC7500 (VIP) encodes the analog video to digital video and
processes the digital video to a digital video stream (CCIR656
format). This output stream (VIP_YUV[7:0]) goes to IC7403
SAA6752H (EMPRESS) and to IC7100 Versatile Stream
Manager. The latter uses the data for VBI (vertical blanking
interval) extraction.
IC7403 (EMPRESS) encodes the digital video stream into a
MPEG2 video stream that is fed to IC7100 (VSM).
Audio Part
I2S audio are sent from the analog board to IC7403 EMPRESS
via connector 1602. The EMPRESS compresses I2S audio
data into an AC3 audio stream which is fed to IC7100 (VSM).
Front-End I2S
IC7100 (VSM) interfaces directly to the different hardware
modules such as Basic Engine, EMPRESS IC7403, MPEG
decoder IC7200 (Sti5508) and buffers the data streams that
are coming from or going to these hardware modules.
In IC7100 (VSM), the video MPEG2 stream and the audio AC3
stream are multiplexed into a I2S packetized stream. The serial
data are sent to the Basic Engine to be recorded.
Loop-Through
The multiplexed audio and video stream in the VSM is fed back
via the parallel front-end interface to IC7200 (Sti5508). This IC
decodes the MPEG stream into analog video and I2S audio.
The video and audio signals are routed to the analog board via
connectors 1601 and 1602. During recording, the recorded
signal is present at the outputs of the analog board.
9.5.2
Playback Mode
During playback, the serial data from the Basic Engine is going
directly to the Sti5505 via the serial front-end I2S interface.
The Sti5508 is a MPEG & Audio/video decoder and has the
following outputs:
•
To the analog board:
–
analog video RGB, YC, CVBS
–
I2S audio (PCM format)
–
SPDIF audio (digital audio output)
•
To the Progressive scan board:
–
digital video YC(7:0).
9.5.3
S2B Interface
The S2B interface between the VSM (IC7100) and the Servo
processor MACE3 controls the Basic Engine during record and
playback mode.
9.5.4
System Clock
System clocks(27MHz) of VSM, Sti5508, EMPRESS and
Progressive Scan are generated by oscillator 7906
9.5.5
Audio Clock
During record mode, the audio clock ACC_ACLK_OSC is
generated by IC7102 (PLL) because then, the audio clock must
be sychronized with the incoming video (VIP_FID) from the
VIP.
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
During playback mode, the audio clock ACC_ACLK_PLL is
generated by the clock synthesizer IC7900 (MK2703S).
Both ACC_ACLK_OSC(also goes to the EMPRESS as
ACLK_EMP) and ACC_ACLK_PLL are fed to the VSM. This IC
selects the appropriate clock to the STI5508. The EMPRESS
IC derives from the incoming ACLK_EMP the I2S audio
encoder clocks AE_BCLK and AE_WCLK which are sent to the
VSM.
9.5.6
On/Off
The digital board is not powered in standby mode. Control
signal ION, coming from the analog board, will enable the PSU
and power the digital board.
•
ION = High: the digital board is in powered down standby
mode
•
ION = Low: the power supply to the digital board is enabled
9.5.7
Reset
Control signal IRESET_DIG, controlled by the microprocessor
on the analog board is sent to the RESET LOGIC circuit.
•
IRESET_DIG = Low in standby mode
•
IRESET_DIG = High: the whole system is reset and the
Digital board is waked up.
9.5.8
I2C Bus
Sti5508 is master of the I2C bus. The following IC's are
controlled by the I2C bus:
•
IC7201 NVRAM
•
IC7403 EMPRESS
•
IC7500 VIP
•
IC7700 FLI2200 Video Deinterlacer Line Doubler
•
IC7801 ADV7196 Video Denc
9.5.9
EMI Bus
The following IC's are connected to the External Memory
Interface bus (EMI) which functions as system bus:
•
IC7301 and 7302: Flash memories which contain the
application and diagnostic software
•
IC7100: VSM
•
IC7200: MPEG AV Decoder
9.
EN 171
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