Pin Description - Philips DVDR980/001 Service Manual

Circuit-, IC Descriptions and List of Abbreviations

5.0 PIN DESCRIPTION

Name Pin Type
AGND Supply
AV Supply
DD
C/LKON CMOS 5 V tol
CNA CMOS
CPS CMOS
CTL0, CMOS 5 V tol
CTL1
D0±D7 CMOS 5 V tol
DGND Supply
DV Supply
DD
Pin Numbers I/O
32, 33, 39, 48, 49, Ð
50
30, 31, 42, 51, 52 Ð
19 I/O
3 O
24 I
4, 5 I/O
6, 7, 8, 9, 10, 11, I/O
12, 13
17, 18, 63, 64 Ð
25, 26, 61, 62 Ð
DVDR980-985 /0X1
Description
Analog circuit ground terminals. These terminals should be tied together
to the low impedance circuit board ground plane.
Analog circuit power terminals. A combination of high frequency
decoupling capacitors on each side are suggested, such as paralleled
0.1 µF and 0.001 µF. These supply terminals are separated from
PLLV and DV internal to the device to provide noise isolation. They
DD DD
should be tied at a low impedance point on the circuit board.
Bus Manager Contender programming input and link-on output. On
hardware reset, this terminal is used to set the default value of the
contender status indicated during self-ID. Programming is done by tying
the terminal through a 10-kΩ resistor to a high (contender) or low (not
contender). The resistor allows the link-on output to override the input.
If this pin is connected to a LLC driver pin for setting Bus Manager/IRM
contender status, then a 10-kΩ series resistor should be placed on this
line between the PHY and the LLC to prevent possible contention. In this
case. the pull-high or pull-low resistors mentioned in the previous
paragraph should not be used. Refer to Figure 9.
Following hardware reset, this terminal is the link-on output, which is
used to notify the LLC to power-up and become active. The link-on
output is a square-wave signal with a period of approximately 163 ns (8
SYSCLK cycles) when active. The link-on output is otherwise driven low,
except during hardware reset when it is high impedance.
The link-on output is activated if the LLC is inactive (LPS inactive or the
LCtrl bit cleared) and when:
a) the PHY receives a link-on PHY packet addressed to this node,
b) the PEI (port-event interrupt) register bit is 1, or
c) any of the CTOI (configuration-timeout interrupt), CPSI
(cable-power-status interrupt), or STOI (state-timeout interrupt)
register bits are 1 and the RPIE (resuming-port interrupt enable)
register bit is also 1.
Once activated, the link-on output will continue active until the LLC
becomes active (both LPS active and the LCtrl bit set). The PHY also
deasserts the link-on output when a bus-reset occurs unless the link-on
output would otherwise be active because one of the interrupt bits is set
(i.e., the link-on output is active due solely to the reception of a link-on
PHY packet).
NOTE: If an interrupt condition exists which would otherwise cause the
link-on output to be activated if the LLC were inactive, the link-on output
will be activated when the LLC subsequently becomes inactive.
Cable Not Active output. This terminal is asserted high when there are
no ports receiving incoming bias voltage.
Cable Power Status input. This terminal is normally connected to cable
power through a 390 kΩ resistor. This circuit drives an internal
comparator that is used to detect the presence of cable power.
Control I/Os. These bi-directional signals control communication
between the PDI1394P25 and the LLC. Bus holders are built into
these terminals.
Data I/Os. These are bi-directional data signals between the
PDI1394P25 and the LLC. Bus holders are built into these terminals.
Unused Dn pins should be pulled to ground through 10 kΩ resistors.
Digital circuit ground terminals. These terminals should be tied together
to the low impedance circuit board ground plane.
Digital circuit power terminals. A combination of high frequency
decoupling capacitors near each side of the IC package are suggested,
such as paralleled 0.1 µF and 0.001 µF. Lower frequency 10 µF filtering
capacitors are also recommended. These supply terminals are
separated from PLLV and AV
DD
isolation. They should be tied at a low impedance point on the circuit
board.
9.
internal to the device to provide noise
DD
EN 285