Pin Numbers - Philips DVDR980/001 Service Manual

Circuit-, IC Descriptions and List of Abbreviations
Name Pin Type
SYSCLK CMOS
TEST0 CMOS
TEST1 CMOS
TESTM CMOS
TPA0+ Cable
TPA0± Cable
TPB0+ Cable
TPB0± Cable
TPBIAS0 Cable
XO, XI Crystal

Pin Numbers

I/O
2 O
29 I
28 I
27 I
37 I/O
36 I/O
35 I/O
34 I/O
38 I/O
59, 60 Ð
DVDR980-985 /0X1
Description
System clock output. Provides a 49.152 MHz clock signal, synchronized
with data transfers, to the LLC.
Test control input. This input is used in manufacturing tests of the
PDI1394P25. For normal use, this terminal should be tied to GND.
Test control input. This input is used in manufacturing tests of the
PDI1394P25. For normal use, this terminal should be tied to GND.
Other vendors' pin compatible chips may require connections and
external circuitry on this pin.
Test control input. This input is used in manufacturing tests of the
PDI1394P25. For normal use, this terminal should be tied to V
Twisted-pair cable A differential signal terminals. Board traces from each
pair of positive and negative differential signal terminals should be kept g
matched and as short as possible to the external load resistors and to
the cable connector.
Twisted-pair cable B differential signal terminals. Board traces from each
pair of positive and negative differential signal terminals should be kept g
matched and as short as possible to the external load resistors and to
the cable connector.
Twisted-pair bias output. This provides the 1.86 V nominal bias voltage
needed for proper operation of the twisted-pair cable drivers and
receivers, and for signaling to the remote nodes that there is an active
cable connection. These terminals must be decoupled with a
0.3 µF±1 µF capacitor to ground.
Crystal oscillator inputs. These terminals connect to a 24.576 MHz
parallel resonant fundamental mode crystal. The optimum values for the
external shunt capacitors are dependent on the specifications of the
crystal used. Can also be driven by an external clock generator (leave
XO unconnected in this case and start supplying the external clock
before resetting the PDI1394P25). For more information, refer to
Section 17.5
9. EN 287
.
DD
g
g