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Circuit-, IC Descriptions and List of Abbreviations
1 Architecture overview
The instruction and data caches are direct-mapped, with a write-back system for the data-cache. The caches support
burst accesses to the external memories for refill and write-back. Burst access increases the performance of page-
mode DRAM memories.
Off-chip
There are two off-chip memory interfaces:
•
The external memory interface (EMI) accessed by the ST20 is used for the transfer of data and programs between
the STi5508 and external peripherals, flash and additional SDRAM and DRAM.
•
Shared memory interface (SMI) controls the movement of data between the STi5508 and 16, 32 or 64 Mbits of
SDRAM. This external SDRAM stores the display data generated by the MPEG decoder and CPU and the C2+
code data.
The EMI uses minimal external support logic to support memory subsystems, and accesses a 32 Mbytes of physical
address space (greater if SDRAM or DRAM is used) in four general purpose memory banks of 8 or 16 bits wide, 21 or
22 address lines, and byte select. For applications requiring extra memory, the EMI supports this extra memory with
zero external support logic, even for 16-bit SDRAM devices. The EMI can be configured for a wide variety of timing and
decode functions by the configuration registers. The timing of each of the four memory banks can be set separately,
with different device types being placed in each bank with no need for external hardware.
1.8
Serial communication
Asynchronous serial controllers
The Asynchronous Serial Controller (ASC), also referred to as the UART interface, provides serial communication
between the STi5508 and other microcontrollers, microprocessors or external peripherals. The STi5508 has four ASCs,
two of which are generally used by the SmartCard controllers.
Eight or nine bit data transfer, parity generation, and the number of stop bits are programmable. Parity, framing, and
overrun error detection increase data transfer reliability. Transmission and reception of data can be double-buffered, or
16-deep FIFOs can be used. A mechanism to distinguish the address from the data bytes is included for multiprocessor
communication. Testing is supported by a loop-back option. A 16-bit baud-rate generator provides the ASC with a
separate serial clock signal.
Each ASC supports full-duplex asynchronous communication where both the transmitter and the receiver use the same
data frame format and the same baud-rate. Each ASC can be set to operate in SmartCard mode for use when
interfacing to a SmartCard.
Synchronous serial control
The Synchronous Serial Controller (SSC) provides a high-speed interface to a wide variety of serial memories, remote
control receivers and other microcontrollers. The SSC supports all of the features of the Serial Peripheral Interface bus
2
(SPI) and the I
C bus. The SSC can be programmed to interface to other serial bus standards. The SSC shares pins
with the parallel input/output (PIO) ports, and support full-duplex and half-duplex synchronous communication when
used in conjunction with the PIO configuration.
1.9
Front-end interface
The STi5508 can be connected to a front-end through the following interfaces:
•
I2S interface;
•
multi-format serial interface;
•
multi-format parallel interface;
DVDR980-985 /0X1
STi5508
9.
EN 231
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