Pacemaker Detection - GE Corometrics 126 Service Manual

Pacemaker Detection

Revision B
Theory of Operation: MECG Board
increasing its input voltage when the ECG output exceeds ±5.7 volts. This allows
the baseline to be rapidly restored when the output offset becomes too large. The
right leg drive is used to feed back to the patient, out-of-phase common-mode
signals, in order to cancel out the effects of these signals.
The output of the two buffer stages in instrumentation amplifier U7 (pins 1, 8)
represents the voltage present at the input leads times a gain of 10. For normal
differential ECG signals, the voltage at these pins is of equal amplitude but opposite
polarity. For common mode signals however, these pins are at equal amplitudes but
the same polarity. Resistors R29 and R30 tie pins 1 and 8 of U7 to the summing
point of the right leg drive integrator stage consisting of U10, C17, and R10. Since
normal signals are of opposite phase at pins 1 and 8 of U7, the current supplied to
the integrator through R29 and R30 is zero, resulting in 0 V output from the right leg
drive. Common mode signals being at the same phase cause the currents to add and
produce an output of opposite polarity to the common mode voltage. This out-of-
phase common mode voltage connects to the patient through R14, a 332 k
which limits the current delivered to the patient under a fault condition. The time
constants used in the integrator were selected for optimum rejection of 50/60 Hz
which is the most frequently encountered common mode noise.
Pacemaker signals are distinguished from normal ECG by the rate of change of the
waveform. Pacemaker pulses have slew rates faster than 100 µs, while the slew rate
of normal ECG signals are typically more than 100 times slower. The pacemaker
detector uses this signal characteristic by differentiating the output of the amplifier/
limiter stage U6 using a high-pass filter consisting of capacitor C28, resistor R50,
and op-amp U5 to separate the pacemaker pulses from the ECG waveform. The
high-pass function from C28 and R50 attenuates the ECG while allowing the
pacemaker pulses to pass through with only minimal reduction in amplitude. The
output of the differentiator is buffered by a section of U5 which is configured as a
unity gain non-inverting amplifier. The buffered output connects to two
comparators formed from two op-amps of U5, one with a positive threshold, the
other with a negative threshold. The positive threshold (+1.0 V) is derived from the
voltage division of the +10 V reference through resistors R49 and R52. The negative
threshold (–1.0 V) is developed by inverting the positive threshold through the last
stage of U5 configured as a unity gain inverting amplifier. When the differentiated
output exceeds one of these thresholds, the associated comparator will toggle
positive. The output of both comparators are ORed through diodes D19 and D20.
When either comparator goes positive, the diode OR gate will turn on transistor Q1
which is used as a level translator from the +15 V output of the comparators to a +5
V logic level. The output from Q1 triggers monostable U3 which generates a 5 ms
pulse that is used by the pacemaker rejection circuitry to gate out the pacemaker
signal. When pacemaker rejection is enabled through a gate in U1, the signal path
from the output of the limiter/amplifier at U6 is altered. The pacemaker enable
comes from control circuitry on the FEGC/UA Board. Instead of connecting to the
original R/C low-pass filter at FET switch U2, the signal from U6 instead is routed
through U2 to an alternate single-pole low-pass filter composed of resistor R40 and
capacitor C38. This filter has a –3 dB point of 100 Hz, however its primary function
is to insert a small delay to the ECG signal to allow for the detection time required
by the pacemaker detection circuitry. This low-pass filter directly drives a slew rate
limiter consisting of diodes D21–D24, resistors R68, R69, capacitor C39, and a
buffer amplifier from an op-amp of U6. To understand how the slew rate limiter
works, the circuit needs to be analyzed from a static condition. With 0 V at the input
of the filter there will be +0.6 V at the junction of D21 and D22, –0.6 V at the
120 Series Maternal/Fetal Monitor
2015590-001
Ω
resistor
4-63