References; Digitrip Rms Trip Assemblies; Type Ds Low Voltage Ac Power Circuit Breakers; Type Spb Systems Pow-R Breakers - Eaton Digitrip RMS 510 LI Instruction Manual

I.L. 29-8858

9.0 REFERENCES

9.1 Digitrip RMS Trip Assemblies

I.L. 29-885 Instructions for Digitrip RMS 510 Trip Unit
I.L. 29-886 Instructions for Digitrip RMS 610 Trip Unit
I.L. 29-888 Instructions for Digitrip RMS 810 Trip Unit
9.2 Type OS Low-Voltage AC Power Circuit Breakers
LB. 33-790-1 Instructions for Low-Voltage Power Circuit
Breakers Types DS and DSL
LB. 33-790-1 Supplement B to Digitrip RMS Trip Units
AD 32-870 Typical Time-Current Characteristic
Curves for Types DS and DSL Circuit
Breakers
SC-5619-93 Instantaneous (I)
SC-5620-93 Long Delay and Short Delay (LS)
SC-5621-93 Ground (G)
508B508 Connection Diagram for Type DS Circuit
Breakers

9.3 Type SPB Systems Pow-R Breakers

I.L. 29-801 Instruction for the Systems Pow-R Breaker
and Drawout Mechanism
I.L. 29-849 Supplementary Instructions for the Sys­
tems Pow-R Breaker used with the Digitrip
RMS Trip Units
AD 29-863 Typical Time-Current Characteristic
Curves for Type SPB Systems Pow-R
Breaker
SC-5623-93 Instantaneous (I)
SC-5624-93 Long Delay and Short Delay (LS)
SC-5625-93 Ground (G)
I.S. 15545 SPB Master Connection Diagram
9.4 Series C ® R-Frame Molded Case Circuit Breakers
29C106 Frame Book
29C107 Frame Instruction Leaflet
Supplementary Instructions for Series C ®
29C713
R-Frame used with the Digitrip RMS Trip
Units
AD 29-167R Typical Time-Current Characteristic
Curves for R-Frame Circuit Breakers
SC-5626-93 Instantaneous (I)
SC-5627-93 Long Delay and Short Delay (LS)
SC-5628-93 Ground (G)
Effective May 1997
Master Connection Diagram for Series C ®
I.L. 29C714
R-Frame Circuit Breaker
APPENDIX A ZONE INTERLOCKING
Assume a ground fault of 2000 Amperes occurs and
refer to Fig A.1.
CASE 1 : There is no Zone Selective Interlocking.
(standard time delay coordination is used)
Fault 3
The branch breaker will trip clearing the fault in
0.1 s.
Fault 2
The feeder breaker will trip clearing the fault in
0 .3 s.
Fault 1
The breaker will trip clearing the fault in 0 .5 s.
CASE 2: There is Zone Selective Interlocking
Fault 3
The branch breaker trip unit will initiate the trip in
0 .03 s to clear the fault and Z3 will send an inter­
locking signal to the Z2 trip unit; and Z2 will send
an interlocking signal to Z1.
Z1 and Z2 trip units will begin to time out, and in
the event that the branch breaker Z3 would not
clear the fault, the feeder breaker Z2 will clear the
fault in 0 .3 s (as above). Similarly, in the event that
the feeder breaker Z2 would not clear the fault, the
main breaker Z1 will clear the fault in 0 .5 s (as
above).
Fault 2
The feeder breaker trip unit will initiate the trip in
0 .03 s to clear the fault; and Z2 will send an inter­
locking signal to the Z1 trip unit. Z1 trip unit will
begin to time out, and in the event that the feeder
breaker Z2 would not clear the fault, the main
breaker Z1 will clear the fault in 0 .5 s (as above).
Fault 1
There are no interlocking signals. The main
breaker trip unit will initiate the trip in 0 .03 s.
Figure A.2 presents a Zone Selective Interlocking con­
nection diagram for a system with two main breakers
from incoming sources and a bus tie breaker. Note the
blocking diode D1 is needed so that the feeder breakers
can send interlocking signals to both the main and tie
breakers, without having the tie breaker send itself an
interlocking signal.
Page 15