Tmds Equalizer Settings; Input Video Pixel Clock Frequency ≤ 170Mhz - Analog Devices ADV7619 Reference Manual

ADV7619 Required Settings Manual

3 TMDS EQUALIZER SETTINGS

Different register settings are required to configure the TMDS Equalizer depending on the resolution received. These required settings are
listed below for the respective resolutions.
3.1 INPUT VIDEO PIXEL CLOCK FREQUENCY ≤ 170MHZ
The following two categories of settings are required for input video resolutions with a pixel clock of less than or equal to 170 MHz.
3.1.1 480i, 576i, 480p and 576p Resolutions up to a 36-bit color depth
The following settings are required to configure the TMDS Equalizer for the 480i, 576i, 480p and 576p resolutions with color depths between
24-bit and 36-bit.
3.1.2 720p, 1080i and 1080p Resolutions up to a 36-bit color depth
The following settings are required to configure the TMDS Equalizer for the 720p, 1080i, 1080p resolutions with color depths between 24-bit
and 36-bit.
HDMI Map
68 85 11
68 86 9B
68 89 03
68 9B 03
68 93 03
68 5A 80
68 9C 80
68 9C C0
68 9C 00
HDMI Map
68 85 10
68 86 9B
68 89 03
68 9B 03
68 93 03
68 5A 80
68 9C 80
68 9C C0
68 9C 00
ADI Required Write
ADI Required Write
ADI Required Write
ADI Required Write
ADI Required Write
ADI Required Write
ADI Required Write
ADI Required Write
ADI Required Write
ADI Required Write
ADI Required Write
ADI Required Write
ADI Required Write
ADI Required Write
ADI Required Write
ADI Required Write
ADI Required Write
ADI Required Write
Rev. 1.8 | Page 7 of 14
ADV7619 Reference Manual