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Circuit Diagrams and PWB Layouts
Digital Board Chrysalis 2.1: 1394
1
2
3
+3V3_IEEE_A
1203
A
SR
52
51
not used
7
8
F1203
6
3283
F1205
5
F1204
10K
4
3
F1202
I207
2
3205
40
F1201
R0
1
6K34
I208
1%
41
R1
VOLTAGE
I209
2200
38
TPBIAS0
1u0
CURRENT
B
GENERATOR
37
TPA0+
36
TPA0-
35
TPB0+
34
TPB0-
C
1.5V
59
XI
XTAL OSC.
F203
1.7V
60
XO
CLOCK
16
43
TRANSMIT
44
DATA
45
ENCODER
D
1201
NC
3253
46
1R0
47
CX-11F
24M576
2204
54
PDI1394P25
100n
2205
55
100n
not used
28
29
50
E
F
5200
I201
+3V3_IEEE_PLL
I202
5202
+3V3_IEEE_A
G
I203
5203
+3V3_IEEE_D
+3V3
H
5204
I204
I
+3V3
always present
1
2
3
DVDR730/0x
4
5
6
+3V3_IEEE_PLL
+3V3_IEEE_D
+3V3_IEEE_D
2235
1n0
7200
42
31
30
27
62
61
26
25
56
PDI1394P25
TESTM
PLLVDD
AVDD
DVDD
I215
24
CPS
15
LPS
RECEIVED
BIAS
23
DATA
ISO_
+3V3_IEEE_D
DECODER/
I216
19
C|LKON
AND
TIMER
2
SYSCLK
1
LREQ
4
3216
LINK
CTL0
INTERFACE
10R
5
CTL1
6
3223
D0
10R
7
D1
8
3228
ARBITR'N
D2
AND
10R
9
D3
CONTROL
3234
STATE
10
D4
MACHINE
10R
11
D5
LOGIC
3238
12
D6
PLL
10R
13
D7
20
3245
PC0
10R
21
PC1
3204
22
PC2
I213
10K
3
CNA
4201
I214
53
RESET_
4202
14
PD
AGND
DGND
PLLGND
49
48
39
33
32
64
63
18
17
58
57
PHY
+5V
not used
+3V3_LINK
7202
PDTC144EU
MPIO23_1394_LED
4
5
6
7.
EN 106
7
8
9
+3V3_IEEE_D +3V3_IEEE_D
+3V3_LINK
I217
3284
1R0
+3V3_LINK
3209
not used
1R0
3220
I211
10R
PHYD0
82
PHYD1
I212
81
3225
80
PHYD2
79
PHYD3
10R
I218
76
PHYD4
75
PHYD5
I219
3231
74
PHYD6
73
PHYD7
10R
I222
86
PHYCTL0
85
PHYCTL1
I225
LINK
3236
87
LREQ
ISOCH & ASYNC
CORE
88
SCLK
I226
10R
91
LPS
56
CYCLEIN
I227
F201
3242
57
CYCLEOUT
55
CLK50
10R
47
1394MODE
48
PD
3248
92
LINKON
93
ISON
10R
+3V3_LINK
+3V3_IEEE_D
22R FOR C2
MPIO8_1394_CNA
42
RESET_
RESET_1394n
CONTROL
AND
49
STATUS
1
50
2
REGISTERS
51
3
52
4
58
5
59
6
72
7
71
8
104
9
TRANSMITTER
65
10
66
11
67
12
68
13
105
14
129
15
144
16
130
17
PCI_AD(31:0)
220R FOR C2
PCI_AD(24)
3297
100R
22
HIFAD0
PCI_AD(25)
3298
100R
21
HIFAD1
PCI_AD(26)
3299
100R
20
HIFAD2
PCI_AD(27)
3315
100R
19
HIFAD3
PCI_AD(28)
3316
100R
16
HIFAD4
PCI_AD(29)
3317
100R
15
HIFAD5
PCI_AD(30)
3318
100R
14
HIFAD6
PCI_AD(31)
3319
100R
13
HIFAD7
+3V3_LINK
4K7
3262
10
HIFD8
4K7
3263
9
HIFD9
4K7
3264
8
HIFD10
4K7
3265
7
HIFD11
4K7
3266
4
HIFD12
4K7
3267
3
HIFD13
4K7
3268
2
HIFD14
4K7
3269
1
HIFD15
I224
38
HIFINT_
MPIO2_1394_IRQn
HIFWAIT
41
33R
3273
3276
1K0
allways present
IC7200 pin 60, F203
A: DC, 1 V/Div, 20ns/Div
+3V3_LINK
7
8
9
10
11
12
13
for DV_IN only
LINK
7201
PDI1394L40
VDD
AV1D0
108
3210
33R
F213
109
3211
33R
AV1D1
F212
3214
33R
AV1D2
110
F211
3215
33R
AV1D3
111
3217
33R
AV1D4
114
F209
12KB BUFFER
AV1D5
115
3218
33R
F208
MEMORY
AV1D6
116
3221
33R
F207
AV1D7
117
3222
33R
AV1CLK
99
3224
82R
F215
AV1FSYNC
100
3229
33R
AV1VALID
102
3227
33R
F205
PACKETS
3235
AV1SY
101
AV1SY
F217
AV1SYNC
103
3226
33R
F214
AV1ENDPCK
98
AV1ENDPCK
F216
3230
AV1ERR0
96
AV1ERR1
97
F200
3219
AV1READY
118
+3V3_LINK
10K
133
3237
33R
AV2D0
MX_D(0)
3239
33R
AV2D1
134
MX_D(1)
3241
33R
AV2D2
135
MX_D(2)
3243
33R
AV2D3
136
MX_D(3)
AV2D4
139
3244
33R
MX_D(4)
AV2D5
140
3246
33R
MX_D(5)
AV2D6
141
3247
33R
MX_D(6)
AV2D7
142
3249
33R
MX_D(7)
AV2CLK
124
3251
33R
AV2FSYNC
125
AV2FSYNC
3255
4K7
AV2VALID
127
3254
33R
ASYNC
AV2SY
126
3259
4K7
AV2SYNC
128
3252
33R
AND
AV2ENDPCK
123
AV2ENDPCK
3256
4K7
AV2ERR0|LTLEND
121
3257
22K
RECEIVER
AV2ERR1|DATINV
122
3258
22K
AV2READY
143
3250
4K7
+3V3_LINK
62
1
63
TESTPIN
2
64
3
PCI_AD(31:0)
220R FOR C2
PCI_AD(0)
HIFA0
33
3202
100R
PCI_AD(1)
HIFA1
32
3260
100R
PCI_AD(2)
HIFA2
31
3274
100R
HIFA3
30
3277
100R
PCI_AD(3)
HIFA4
29
3278
100R
PCI_AD(4)
HIFA5
28
3279
100R
PCI_AD(5)
8-BIT
HIFA6
27
3294
100R
PCI_AD(6)
HIFA7
26
3295
100R
PCI_AD(7)
INTERFACE
HIFA8
25
3296
100R
PCI_AD(8)
220R FOR C2
HIFSC_
36
I223
3272
100R
HIFWR_
37
I220
3270
100R
220R FOR C2
HIFALE
39
I221
HIFRD_
40
3271
100R
220R FOR C2
HIF16BIT
45
HIFMUX
46
4203
+3V3_LINK
not used
GND
4204
I205
BOARD_ID
MPIO9_BOARD_ID_0
MPIO10_BOARD_ID_1
MPIO11_BOARD_ID_2
MPIO12_BOARD_ID_3
10
11
12
13
14
1201 D1
3289 H13
1203 A1
3290 I13
2200 B2
3291 I13
2201 C2
3292 I13
2202 D1
3293 I13
2203 D2
3294 F12
2204 D2
3295 F12
2205 D2
3296 F12
2206 G3
3297 F8
2207 F2
3298 F8
2209 G2
3299 F8
2210 G2
3315 F8
2212 H1
3316 F8
A
2214 H2
3317 F8
2215 H2
3318 F8
2217 I2
3319 F8
2218 I2
3320 F13
2219 I3
4201 D6
2220 I3
4202 D6
2221 I3
4203 G12
2222 I3
4204 G12
2223 I4
4205 A4
2224 I4
5200 F2
2225 I4
5201 F5
2226 I5
5202 G2
B
2227 I5
5203 H2
2228 I5
5204 I1
2229 I5
6200 G4
2230 I6
7200 A5
2231 I6
7201 B12
2232 I6
7202 H5
L_D(7:0)
2233 I7
F1201 B1
2234 I7
F1202 A1
L_D(0)
2235 A5
F1203 A1
L_D(1)
2236 G3
F1204 A2
L_D(2)
2237 B9
F1205 A2
F210
L_D(3)
2238 B6
F200 D12
L_D(4)
3200 E6
F201 C9
L_D(5)
C
3202 F12
F203 C3
L_D(6)
3203 H5
F204 C13
F206
L_D(7)
L_CLK
3204 D6
F205 C13
F204
L_FSYNC
3205 A2
F206 C13
L_VAL
3206 B7
F207 C13
10K
3207 B8
F208 C13
L_SYNC
3208 B7
F209 C13
10K
L_D_CTL
3209 B8
F210 C13
3210 C12
F211 C13
3211 C12
F212 C13
3212 B2
F213 C13
3213 B3
F214 C13
3214 C12
F215 C13
D
3215 C12
F216 D13
MX_D(7:0)
3216 B6
F217 C13
3217 C12
I200 H4
3218 C12
I201 F2
3219 D13
I202 G2
3220 B7
I203 H2
3221 C12
I204 I2
MX_D_CTL
3222 C12
I205 H11
3223 B6
I206 G4
MX_CLK
3224 C12
I207 A3
3225 C7
I208 B3
MX_VAL
3226 C12
I209 B3
3227 C12
I210 C2
E
MX_SYNC
3228 C6
I211 B7
3229 C12
I212 C7
3230 D13
I213 D6
3231 C7
I214 D6
3232 C2
I215 A6
3233 C2
I216 B6
3234 C6
I217 A8
3235 C13
I218 C7
3236 C7
I219 C7
3237 D12
I220 G12
3238 C6
I221 G12
3239 D12
I222 C7
+3V3_LINK
F
3240 C2
I223 G12
3241 D12
I224 G8
3242 C7
I225 C7
3243 D12
I226 C7
3244 D12
I227 C7
3245 D6
3246 E12
3247 E12
XIO_SEL1
PCI_CBE(1)
3248 D8
3249 E12
PCI_CBE(2)
3250 E12
3251 E12
3252 E12
G
3253 D2
3254 E12
3255 E13
3256 E13
3257 E13
3258 E13
3259 E13
3260 F12
3261 E3
3262 F8
3263 F8
3264 F8
3265 G8
H
+3V3
3266 G8
3267 G8
3268 G8
3269 G8
3270 G12
3271 G12
3272 G13
3273 G8
3274 F12
3275 G5
3276 G7
3277 F12
3278 F12
I
3279 F12
3280 A7
3281 A7
3282 A8
3283 A2
3284 A8
3285 A6
3286 H13
3287 H13
TR 19003_001
3288 H13
250504
14
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