Smb5: I/O Status; Smb6: Cpu Id Register; Smb7: Reserved - Siemens Simatic S7-200 System Manual

S7-200 Programmable Controller System Manual

SMB5: I/O Status

As described in Table D-6, SMB5 contains status bits about error conditions that were detected in the I/O
system. These bits provide an overview of the I/O errors detected.
Table D-6
SM Bits
SM5.0
SM5.1
SM5.2
SM5.3
SM5.4 to
SM5.7

SMB6: CPU ID Register

As described in Table D-7, SMB6 is the identification register for the S7-200 CPU. SM6.4 to SM6.7 identify
the type of S7-200 CPU. SM6.0 to SM6.3 are reserved for future use.
Table D-7
SM Bits
Format
SM6.0 to
SM6.3
SM6.4 to
SM6.7

SMB7: Reserved

SMB7 is reserved for future use.
D
410
Special Memory Byte SMB5 (SM5.0 to SM5.7)
Description (Read Only)
This bit is turned on if any I/O errors are present.
This bit is turned on if too many digital I/O points have been connected to the I/O bus.
This bit is turned on if too many analog I/O points have been connected to the I/O bus.
This bit is turned on if too many intelligent I/O modules have been connected to the I/O bus.
Reserved.
Special Memory Byte SMB6
Description (Read Only)
MSB
7
x x x x r r r
Reserved
xxxx = 0000 = CPU 222
0010 = CPU 224
0110 = CPU 221
1001 = CPU 226/CPU 226XM
LSB
0
CPU ID register
r