Interfacing; Microprocessor Clock Synthesizer - Motorola MCS 2000 Service Instructions Manual

Controller Section Theory of Operation: Interfacing
The D/ A line CUR LIM SET at U0551 pin 4 adjusts the maximum allowed current by creating an
offset voltage equivalent to the voltage drop across the sense resistor (R5612). For all models
(except UHF1 110W and UHF2 40W), CUR LIM SET connects to the non-inverting input of U0550-2
(pin5) through resistors R0547 and R0583, reducing the voltage at the non-inverting input sufficiently
to make the non-inverting and inverting inputs equal at the desired current drain. Then, if additional
current passes through the sense resistor, CURRENT SENSE- will be reduced causing OP AMP
U0550-2 to drive high through R0556 and CR0550, reducing power and current. For UHF1 100 W
and UHF2 40 W, CUR LIM SET connects to the inverting input of U0550-2 (pin5) through resistors
R0547 and R0583. This circuit modification improves the over-voltage protection, but causes Current
Limit Tuning Softpot Values to have an inverse relationship. Increasing the softpot value for UHF1
100 W and UHF2 40 W decreases the current limit (increasing power), but for all other radios,
increasing the softpot value increases the current limit (decreasing power).
PA control voltage limit consists of a portion of the control voltage fed back to the power control loop.
PA_CNTL_LIM is produced by a voltage divider network on the PA board. When PA_CNTL_LIM
goes above the reference voltage of 4.65 V plus one diode voltage drop (i.e. 0.7 V) then protection
begins. At this point the control voltage PA_CNTL is clamped. This protects the PA from being driven
too hard by PA_CNTL which could cause excessively high output power.

Interfacing

(Refer to "Figure 7-1. Clock Distribution Block Diagram" on page
general reference)

Microprocessor Clock Synthesizer

(Refer to ASFIC schematic page 10-27 for reference)
The clock source for the microprocessor system is generated by the ASFIC (U0200). Upon power-up
the reference oscillator U5800 (Pendulum) provides a 16.8 MHz reference. Based on this reference
the synthesizer (U5801) generates a 2.1 MHz waveform that is routed from the RF section (via
C0403) to the ASFIC (on U0200-E1) and the option connectors (J0401-3 and J0408-3). At the option
connectors the 2.1 MHz may be used as a reference for any option boards that are attached. For the
main board controller the ASFIC uses 2.1 MHz as a reference input clock signal for its internal
synthesizer. The ASFIC, in addition to audio circuitry, has a programmable synthesizer which can
generate a synthesized signal ranging from 1200 Hz to 32.769 MHz in 1200 Hz steps.
When power is first applied, the ASFIC will generate its default 3.6864 MHz CMOS square wave µP
CLK (on U0200-D1) and this is routed to the microprocessor (U0103-36) and SLIC (U0104-A3). After
the microprocessor starts operation, it reprograms the ASFIC clock synthesizer to a higher µP CLK
frequency (usually 14.7456 MHz) and continues operation.
The ASFIC synthesizer loop uses C0208, C0209 and R0204 to set the switching time and jitter of the
clock output. If the synthesizer cannot generate the required clock frequency it will switch back to its
default 3.6864 MHz output.
Because the ASFIC synthesizer and the µP system will not operate without the 2.1 MHz reference
clock it (and the voltage regulators) should be checked first in debugging the system.
68P81083C20-D
10, and Interface schematic page 10-28 for
7-9
December 6, 2004