Pal Demodulator, Y Trap Circuit (Bd Board) - Sony BVM-1916 Operation And Maintenance Manual

(BVM-2016P ONLY)
3-10. PAL DEMODULATOR, Y TRAP CIRCUIT
(BO BOARD:Serial N0.2000382 and Higher)
The composite video signal ( PAL) ~upplied from BA board
i,
fed to
transistor Ql (buffer). then is supplied to the 4.43 MHz trap cm:uit
with Y signal and to band pass filter v.ith chrominancc signal
3-10-1. Chroma Band Pass Filter
The composite video signal obtained from at the emitter of tran-
'iistor Ql is fed to the Band pas, filter composed of re~istor Rl2,
capacitor C7, CB, inductor L3 and transistor Q5.
The center frequency of this filter is adjusted to the subcarrier
frequency (4.43 MHz) by L3. and chrominance signal is denvied
from Q5.
3-10-2. Residual SW Circuit
The chrominance signal derivied at transistor QS is fed to analog
switcher 1(2
When switch S ! on BJ board is set to ON position, residual pulse
which has almost same phase as H sync is fed to control terminal
of analog switcher (pin
G)
of IC2) and screening is performed
during H sync period.
When switch SI on BJ board is set
to
OFF position,
LO'-V
level signal
(OV DC) is fed to control terminal and screening actlon 1s not per-
formed. Thus residual switch circuit does·not activate
When there is residual subcarrier in the \'!deo signal, damp ievd ot
color difference signal changes by turning switch SI ON/OFf and
therefore re,idual subcarrier can be checked on the piL·:1.::-e 1s
a
color shift
3-10-3. Chroma Amplifier Circuit
The chrominance signal from residual switch circuit (IC2 pin
@ )
is
fed to chroma amplifier circuit (017, Q36).
After the chroma signal is amplified by the inversion amplifier
(gain: IX), it is voltage divided by resistors R400 and R314 and
then input to the R-Y input terminal (ICI, pin@) and B-Y input
terminal (!Cl, pin
@)
of the following demodulator circuit via the
buffer (Q38).
3-10-4. Phasa Control Circuit
The chrominance signal from residual switch is also fed to phase
control circuit (Q6, Q?, Q8, Q9, D10).
In this circuit, a variable capacitance diode (D10) 1s used to control
the phase of color burst signal.
Anode voltage of D10 is applied by variable resi,tor RV8 and pre,et
adjustment of phase is made by this variable resistor
When the PHASE control on the right side of the front panel is
turned, DC !eve! of phase control signal (board terminal Al3)
changes and this phase control signal is fed to the cathode of Dl0
via analog s\vitcher (IC5). In this way, Bur~t phase of chrommance
signal is controlled according to the DC level of the phase control
,ignal.
When PAL-D i, ,elected with the PAL <;witch inside the right side
drawer, between pins
G)
and
©
of JCS becomes conductive and
phc1se control become, dependent on RV7, disabling the Phastc
Control of the right side front panel.
3-21
Analog switcher JCS (l/3) activate~ to make ~hort-c1rcu1t between
input terminal pin
G) or(])
and output terminal pin
G),
only when
COLOR STANDARD SELECTOR in the right \Jde of drawer is
selected to PAL and otherwise pin® kept open circuit
As above phase controlled chrominance signal is derived from
collector of transistor Q9 :,nd burst signal in this signal is gated by
IC6. The gated burst ~ignal is fed to the burst input terminal pm
@
of demodulator IC!.
3-10-5.
PAL Demodulator
Block diagram of IC used for PAL demodulator is shown in FigureU.
This IC is designed for u,e of ~TSC demodulator.
When chrom~ance signal is fed to pin
Ci)
and pm
0 .
color burst
signal to pin
@
and Burst Gate Pulse (B.G.P.) to plJl
(U) .
R-Y and
B-Y color difference signals Jre obtained at output terminals pin@,
and pin
@
The demodulation a.,es of this demodulator are R-Y ,n.i~ anri B-Y
a--.is. Variable capacitor CV] 1s adjusted so that the ph:,sc angles
between them are 90'=·
Local oscillator (4.43 MHz) 1s form<:d by C\\i o~c1llator in IC!
connected to the terminal pin(I),@.(I). @Jnd external cncuit.
The variable c:,pacitor CV2 is adjusted ~o that the free run frequen-
cy may be ~ubcarrer frequency 4.433619 MHz
Also APC (Automatic Pha\l' Control) cJrcu1t i, form.:d by APC
\ectmn
in
IC] connected to tl1L· !L'rmmal pm
®
and
@
local oscillator is controlled by APC circuit
The color difference signals demodulated hy this IC are fed to lo,,._
pass filter, where high frequency component
h
removed. then R-Y
and B-Y color difference signals are obtained
Block diagram of PAL demodulator
Figure 16
3-10-6. PAL-D Matrix and PAL S/D Switching Circuit
This circuit is further divided into orcuit~ for thl' R-Y and B-Y
signals. but the operation of both circuits is the same. So only the
R-Y on<: will be explained.
R-Y signals input from the demodulator circuit are input
to
Q20
(BUFF) and Q2l (BCFF).
The signals input to Q21 are then input to pin
@
of the analog
switcher (ICS). When PAL S has been selected, between pins
@
and
®
becomes conductive and the signals are supplied to the
following circuit via Q33 (BUFF).
The signals input to Q20 are formed by IC? and QI8.
Bias is controlled by a clamp circuit and is input to pin
CD
of the
IH delay line (IC3). The DC level of the input is adjusted to the
optimum value by using RV9.
JC3, driven by the 17.715 MHz clock signal generated by the clock
generator circuit configured with X2, 034 and Q35, delays the
input signal by lH cycle and outputs it from pin
0).
The high frequency component of the signal thus output is removed
by the low-pass filter configured with Q40, Q22 and Q23, after
which the signal is input to the following PAL-D matrix circuit.
The PAL-D matrix circuit is configured with RIO0, RI0I and Q24.
The signal that was not delayed is input through RI00 while the IH
delayed signal is input through Rl0I at a ratio of 1/2.
The PAL-D signal added to the base of Q24 is obtained from its
emitter. The signal obtained from the Q24 emitter is input to pin
@ of JCS. When PAL-D is selected, between pins
@)
and @
becomes conductive and the signal is supplied to the following
circuit via Q33 (BUFF).
3-10-7. 4.43
MHz
Trap Circuit,
Phasa
Compensation, Y
Delay Conrrection Circuit
The composite video signal from the emitter of transistor QI is fed
to 4 43 \1Hz trap circuit composed of resistor R3, R4, RS. capacitor
Cl. (2 and inductor LI
Adjustment of LI is made so that the resonance frequency of this
trap circuit should be subcarrier frequency.
Y (luminance) signal removed subcarner is obtained at output
terminal of the trap circuit and is fed to the phase compensation
circuit. (Transistor 02, resistor R6, R7, R8. inductor L2 capacitor
C4)
This circuit compensates phase delay of the signal at high frequency
due to the trap circuit.
Y signal compensated phase delay is fed to Y-delay circuit In this
circuit Luminance/Chrominance time error is compensated by delay
line
3-10-8. Color Standard Selector
When PAL ,yqem
1~
not ,elected h} the COLOR STANDARD
SELECTOR in the right ~idc drnwer. transistor QI0I. QJ02 arc cut
off and
~
12V line pO\vn rnurce
h
not ,upplle<l to the demodulator
ClTCUlt
BLOCK DIAGRAM OF BO (PAL) BOARD
8.G.P
luo(PAL
DECODE:, y TRAP)
I
IC511/31
PHASE CONT 13 PKj\,SE CONTROL
SYSTEM 6,
PAL S/O SWITCH
"' f
PAL -S PKj\,S[
I
PRESET
j\,QJ
"
VIDEO IN
~10[0 IN
PIJRE. C
PURE. C
RESP
PAL SID SW All
COMB. SW 89
C.CL.P
s.s
p
+
12V
-12V 4.43MH1
SANO PASS ADJ
"
er, s
L3,Rl2
SYSTEMIPALI SW
CONTROL
.,,
REGULATOR
3-22
RVIO
8-Y CLAMP
LEVEL
R- Y OUT
R-Y
our
KILLER
B-Y OUT
1 8-Y OUT
AS Y
OVT
88 Y OUT