Sync Precessor, Pulse Generator (Bj Board) - Sony BVM-1916 Operation And Maintenance Manual

Trinity color video monitor
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3-5. SYNC PROCESSOR, PULSE GENERATOR
(BJ
BOARD)
3-5-1. 1H Pulse Processing
The composite sync is separated from incoming signal at BA board.
And 1 H sync is made by separating V sync and equalizing pulse
from composite sync.
Also H sync which has constant pulse width is made from lH
sync.
3-5-2. 2fH Multivibrator
This circuit generates 2fH rate pulse from H rate-flyback pulse.
3-5-3. Vertical Counter
The 2fH rate pulse is counted down to generate Vertical rate trigger
pulse for vertical deflection circuit.
When there is no incoming signal, trigger pulse is generated by
vertical counter (384H).
When there is incoming signal with V sync, this counter circuit is
reset by V sync and generates trigger pulse synchronized with V
sync.
Also in order to increase stability of vertical scanning, noise gating
process is made during V sync period.
3-5-4. V Sync and Delay
V sync and V BLANKING pulses are generated by output trigger
pulse from vertical counter.
And when V DELAY SW on the front panel is selected ON, these
pulses are generated in a V /2 delayed position relative to the V
sync position of incoming signal.
3-5-5. Crosshatch Generator
Internal crosshatch signal is made as follows.
The vertical lines are generated by approx. 18fH rate pulses syn-
chronized with flyback pulse.
And flyback pulse is ·counted down to generate horizontal lines.
3-5-6. Burst Gate Pulse, Y-CLAMP Pulse, C-CLAMP Pulse
Generator
The Burst Gate Pulse (B.G.P.), clamp pulse for luminance signal
(Y.CLP) and clamp pulse for color difference signal (C.CL.P) are
generated from lH sync via LCR network and transistors.
3-5-7. Picture Set Up Pulse Generator
This is the gate pulse generator for picture set-up function, and
consists of mono multipliers.
3-5-8. Split, Y Blanking, C Blanking Pulse Generator
Y BLANKING pulse (Y BLK P) and C BLANKING pulse (C BLK P)
are generated. These pulses are used for the purpose of DC restora-
tion of color difference signal, Y signal and RGB signal. DC restora-
tion is made by inserting the black reference signal during blanking
period in the signal. Also C.BLK. pulse is mixed with vertical rate
blanking signals for SPLIT display and for B/W display.
3-5-9. Horizontal Rate AGC and Clamp Pulse Generator
COLOR GAIN control, CONTRAST control and BRIGHTNESS
control are stabilized by insertion
of reference signal and using
feedback
circuit. Horizontal
rate BLACK pulse (B.P), BLACK
CLAMP pulse (B.CL.P) and WHITE CLAMP pulse (W. CLP) are
generated here.
3-9
3-5-10.
Vertical Rate AGC and Clamp Pulse Generator
In this model, BEAM CONTROL circuit is used for high stability
in white balance.
The reference signal is inserted in the signal for gain control circuit
in video output
amplifier and for beam control circuit. Vertical
rate pulses are used for this purpose.
Vertical rate BEAM PULSE (BM.P) DRIVE PULSE (DRIVE.P) and
BEAM CLAMP PULSE (BM.CLP) are generated here.
3-5-11. Others
Black reference is determined at the position of clamping in black
reference insertion circuit for both color difference signal and
RGB signal. Accordingly C.CLP is used as clamp pulse for color
difference signal processing and Y.CL.P is for RGB signal. CLAMP
PULSE SELECTION SW switches C.CLP. or Y CL.P to the clamp
pulse for the insertion of black reference.
BLOCK DIAGRAM
OF BJ BOARD
~--------------------
-------------------------
I C4, 7,1911/41,20, 21(4/41,2212/4,3)1) IC23{3/3l
IC3,5,9(1/2l 1912/4) 21
(2.-1
~
'"22(4/4) 23(1/3,2/31,24(1/6,2/61,D8
I C2 ( 1-3/4), 16 ( 1/41, 17, 18, 24(2/6 ,3/6), 25(5/6,6/6)
IC27(2/3) ,28,Q 14, DI, I CII ( 1/2)
l~~~--'~'-o_o,_,
____
~~1----+J·:
V SYNC
a DELAY
l._ __
__,_1.__~t,--c-R_o_,'.f~'-H_'_'_'_H_o_,_N_._~~~_Jf-
L _____
_j~:2~:
i--,~::,:,....--1
/
l~E
H1;;'JLsE
f
:
2
,
H'.·,\
5
Nc
POSITION
INTERVAL
-'
IC251~/6)
83
CL. P. SW
....,.
A4
AFC.P
84
H.OL.SW
-.A5
V.SYNC
85
POWER LEO
I
A6
H.8LK.P
1Cbl2/2l,19(3/4l,22(1/4l
D9
I
ca'
912/21 191414)1 IC25{1/61
IC6( I /2), 10( I/ 21, 13, 29
015-18, 25, 26
1(2711/31
L_
B6
7
50/60
SW
I
I
I
2!H
MULTI
I
I
,c,
ICl3{4/4 l
I
PIC, SET PULSE
GEN
RESIDUAL
PULSE
GEN
I
I
7
s,
RES.SW
j
ICI 1(2/21
ICl4
(l/43/44AJ
ICl6I4/4),
2415/61
IH PULSE
DISPOSAL
r-
SPLIT,
Y BLANKING, C BLANKING,
PULSE
GEN
BURST GATE,Y-CLJ\MP,C-CLAMP
PULSE
GEN
I
Y.CLF
CLAMP
s(J~i\wl
t
c
C,B
,f ""
8.G.P
B.G.P
POSITION
WIDTH
L
ICIOl2/2I
, 019"'-24 , D2 3
IC27{3/3l
H
CYCl,E AGC
a
CLAMP PULSE GEN
I
HORV
~
DL.SW
t "'
B.<
WIOTH
ICl2,l5,
1612/4), 2111/4) ,26
1:,,,'-,--~~____,1
~
V CYCLE AGC
&
CLAMP PULSE GEN
IC16l3/41 25(3/6)
L....:_I
HOR V
I
IV.BL.K..f1 BLK·. p
I
POSITION
BJ (
SYNC PROCESSING
PULSE GEN
---------------'!!!!!!:'--=-
3-10
I
KILLER
B7
CH. OUT
8
V.DL.SW
-
88
COMP SYNC
/\9
RES.P
89
CH.SW
I
DL.SW
"
"
SPLIP SW
G. V. S
Al
B. G. P
I
Y. CL. P
Al3
C,CL .P
13
N/V
SW
s,
6
D.AFC.P
C.8LK.P
HV.BLK. P
Y.8LK.P
6
B.P
17
W.CL.P
I
8 .CL. P
18
BM.P
-,~"!-.,!'.D.~C~C~.
~p-~
____,
19
BM.CL.
P
I
DRI\/E.P
- "'
"'
+
I2V
+
12V
PIC.S.SW
PIC.S.VR
GND
GND

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