Pal Demodulator, Y Trap Circuit (Bo Board) - Sony BVM-1911 Operation And Maintenance Manual

(BVM-2011 P ONLY)
3-9. PAL DEMODULATOR, Y TRAP CIRCUIT
(BD BOARD)
The composite video signal ( PAL) supplied from BA board is fed to
transistor Ql (buffer), then is supplied to the 4.43 MHz trap circuit
with Y signal and to band pass filter with chrominance signal.
3-9-1. Chroma Band Pass Filter
The composite video signal obtained from at the emitter of tran-
sistor QI is fed to the Band pass filter composed of resistor RI 2,
capacitor C7, C8, inductor L3 and transistor QS.
The center frequency of this filter is adjusted to the subcarrier
frequency (4.43 MHz) by L3, and chrominance signal is derivied
from QS.
3-9-2. Residual SW Circuit
The chrominance signal derivied at transistor QS is fed to analog
switcher IC2.
When switch S 1 on BJ board is set to ON position, residual pulse
which has almost same phase as H sync is fed to control terminal
of analog switcher (pin
Q)
of IC2) and screening is performed
during H sync period.
When switch SI on BJ board is set to OFF position, Low level signal
(0V DC) is fed to control terminal and screening action is not per-
formed. Thus residual switch circuit does not activate.
When there is residual subcarrier in the video signal, clamp level of
color difference signal changes by turning switch SI ON/OFF and
therefore residual subcarrier can be checked on the picture as a
color shift.
3-9-3. Chroma Amplifier Circuit
The chrominance signal from residual switch circuit (IC2 pin@) is
fed to chroma amplifier circuit (Ql 9, Q36).
After the chroma signal is amplified by the inversion amplifier
(gain: lX), it is voltage divided by resistors R400 and R314 and
then input to the R-Y input terminal (!Cl, pin (3)) and B-Y input
terminal (!Cl, pin (2)) of the following demodulator circuit via the
buffer (Q 3 8).
3-9-4. Phasa Control Circuit
The chrominance signal from residual switch is also fed to phase
control circuit (Q6, Q7, Q8, Q9, 012).
In this circuit, a variable capacitance diode (010) is used to control
the phase of color burst signal.
Anode voltage of 010 is applied by variable resistor RVS and preset
adjustment of phase is made by this variable resistor.
When the PHASE control on the right side of the front panel is
turned, DC level of phase control signal (board terminal Al3)
changes and this phase control signal is fed to the cathode of DI 0
via analog switcher (ICS ). In this way, Burst phase of chrominance
signal is controlled according to the DC level of the phase control
signal.
When PAL-D is selected with the PAL switch inside the right side
drawer, between pins
Q)
and
G)
of ICS becomes conductive and
phase control becomes dependent on RV7, disabling the Phase
Control of the right side front panel.
3-19
Analog switcher !CS (1/3) activates to make short-circuit between
input terminal pin
Q)
or
G)
and output terminal pin@, only when
COLOR STANDARD SELECTOR in the right side of drawer is
selected to PAL and otherwise pin
G)
kept open circuit.
As above phase controlled chrominance signal is derived from
collector of transistor Q9 and burst signal in this signal is gated by
IC6. The gated burst signal is fed to the burst input terminal pin
@
of demodulator IC I.
3-9-5. PAL Demodulator
Block diagram of IC used for PAL demodulator is shown in Figure E.
This IC is designed for use of NTSC demodulator.
When chrominance signal is fed to pin
G)
and pin
Q) ,
color burst
signal to pin
@
and Burst Gate Pulse (B.G.P.) to pin
@ ,
R-Y and
B-Y color difference signals are obtained at output terminals pin@
and pin
@
The demodulation axes of this demodulator are R-Y axis and B-Y
axis. Variable capacitor CV! is adjusted so that the phase angles
between them are 90°.
Local oscillator (4.43 MHz) is formed by CW oscillator in !Cl
connected to the terminal pinG),
iJ)
,Q),
®and external circuit.
The variable capacitor CV2 is adjusted so that the free run frequen-
cy may be subcarrer frequency 4.43 36 I 9 MHz.
Also APC (Automatic Phase Control) circuit is formed
section in !Cl connected to the terminal pin
@
local oscillator is controlled by APC circuit.
by APC
@
and
The color difference signals demodulated by this IC are fed to low
pass filter, where high frequency component is removed, then R-Y
and B-Y color difference signals are obtained.
Block diagram of PAL demodulator
Figure E
3-9-6. PAL-D Matrix and PAL S/D Switching Circuit
This circuit is further divided into circuits for the R-Y and B-Y
signals, but the operation of both circuits is the same. So only the
R-Y
one will be explained.
R-Y signals input from the demodulator circuit are input to Q20
(BUFF) and Q21 (BUFF).
The signals input to Q21 are then input to pin
G)
of the analog
switcher (]CS). When PAL S has been selected, between pins
G)
and
@
becomes conductive and the signals are supplied to the
following circuit via Q33 (BLFF).
The signals input to Q20 are formed by IC7 and Q 18.
Bias is controlled by a clamp circuit and is input to pin
@
of the
lH delay line (IC3). The DC level of the input is adjusted to the
optimum value by using RV9.
IC3, driven by the 10.64 MHz clock signal generated by the clock
generator circuit configured with XZ, Q34 and Q3S, delays the
input signal by 1 H cycle and outputs it from pin
@ .
The high frequency component of the signal thus output is removed
by the low-pass filter configured with Q22 and Q23, after which
the signal is input to the following PAL-D matrix circuit.
The PAL-D matrix circuit is configured with Rl00, Rl0I and Q24.
The signal that was not delayed is input through RI 00 while the 1 H
delayed signal is input through R!0l at a ratio of 1/2.
The PAL-O signal added to the base of Q24 is obtained from its
emitter. The signal obtained from the Q24 emitter is input to pin
(I)
of JCS. When PAL-O is selected, between pins
G)
and
@
becomes conductive and the signal is supplied to the following
circuit via Q33 (BUFF).
3-9-7. 4.43 MHz Trap Circuit, Phasa Compensation, Y
Delay Conrrection Circuit
The composite video signal from the emitter of transistor Q 1 is fed
to 4.43 MHz trap circuit composed of resistor RS, R6, R7, capacitor
Cl, C2 and inductor L 1.
Adjustment of LI is made so that the resonance frequency of this
trap circuit should be subcarrier frequency.
Y (Luminance) signal removed subcarrier is obtained at output
terminal of the trap circuit and is fed to the phase compensation
circuit. (Transistor Q2, resistor R8, R 9 RI 0, inductor L2 capacitor
C4)
This circuit compensates phase delay of the signal at high frequency
due to the trap circuit.
Y signal compensated phase delay is fed to Y-delay circuit. In this
circuit Luminance/Chrominance time error is compensated by delay
line.
3-9-8. Color Standard Selector
When PAL system is not selected by the COLOR ST AND ARD
SELECTOR in the right side drawer, transistor Q 101, Q 102 are cut
off and
±
I 2V line power source is not supplied to the demodulator
circuit.
BLOCK DIAGRAM OF BD (PAL) BOARD
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GENERATOR
3-20
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INPUT
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R-T O'JT
R-Y OUT
KILLER
B-Y
our
S-Y OUT