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1-11. Contrast, Bright Adjustment Circuit
The R signal is contrast-adjusted
by IC I 12 (gain control
amplifier). The R signal output from !Cl 12 and amplified by
QI 67 to QI 69, input to IC! I 3 (1/3). and the voltage of the 100
IRE pulse is sample-held. At !Cl 14 (1/2), this voltage and the
CONT voltage are compared, and the IC! 12 gain is controlled.
As a result, the 100 IRE pulse and CONT voltage becomes
equal. Consequently, by varying the CONT voltage, the contrast
level can be adjusted. The
R
signal output from QI67 to Ql69
is also input
to
IC! 13 (2/3). Here, the voltage of the SET UP
pulse is sample-held. At !Cl 14 (2/2), this voltage and the GND
level is compared to control the DC bias of ICI 12. As a result.
the pedestal level of the R signal is fixed at the GND level.
The DC bias of the R signal amplifier
(Q 167 to QI 69) is
controlled by the BRT voltage to adjust BRIGHT.
At IC701 ( 1/3), the BRT voltage is created by switching the
BRIGHT voltage and BRT CENTER voltage in the period
insened with the pulse (IOOIRE pulse, and SET UP pulse) and
in other periods.
The same is performed for the B and G signals.
1-12. Pulse Insertion Circuit
At !Cl 16, The BIAS REF pulse, DRIVE REF pulse, and
character pulse are inserted in the R signal. The level of the
BIAS REF pulse is set by the BIAS REF voltage. The level of
the DRIVE REF pulse is set by the DRIVE REF voltage.
The same is performed for the B and G signals.
1-13. Drive Control Amplifier
To prevent the drive current of the CRT cathode from exceeding
the reference value, and the drive voltage from exceeding the
reference
value, the levels of the R, G, and B signals are
controlled.
The dri"e current of the CRT cathode is detected by the current
of Pin
Q)
of the VIDEO OUT amplifier (IC 119). The current of
Pin
@
is clamped, IN-converted
by IC123 (2/2), sampled by
IC 126 (2/3), and compared
with the reference
voltage (R
DRIVE !K) at IC127 (2/2). When the drive current exceeds the
reference value, the signal output from IC 127 (2/2) is passed
through !Cl 17 (3/3), Q170 to QI72, and input to IC! 15 (R
drive control amplifier) to lower its gain.
The dri "e voltage of the CRT cathode is detected by the voltage
of Pin
(!)
of the VIDEO OUT amplifier (IC I 19). The voltage of
Pin
®
is clamped by ICI21 (1/2), sampled by ICI26 (1/3), and
compared with the reference voltage (R DRIVE V) at IC127 (1/
2). When the drive voltage exceeds the reference value, the
signal output from IC!27 (1/2) is passed through IC! 17 (3/3)
and Q 170 to Ql72 and input to ICI 15 (R drive control
amplifier) to lower its gain.
3-2
The SUB CPU (IC902) sets whether to control the drive amount
based on the drive current (current mode) or control the drive
amount according to the drive voltage (voltage mode) (IK/V
SW). Normally, the SUB CPU operates in the voltage mode and
sets into the current mode during WB adjustment. The DRIVE
CO~P
is used for converting
the data of DRIVE V in the
voltage mode, and the data of DRIVE IK in the current mode.
1-14. Clamp Circuit (3)
The voltage of the BLACK pulse of the R signal is sample-held
by !Cl 17 (2/3). At IC! 18 (1/2), this voltage and the GND level
are compared and the DC bias of the R signal amplifier (Ql74
to Ql76) is controlled. As a result, the pedestal level of the R
signal is fixed at the GND level.
The same is performed for the G and B signals.
1-15. Cut-Off Switch
At IC! 17 (1/3), the VIDEO TIMING pulse is used to switch
between the R signal and cut-off voltage (-0.3 Vdc).
The same is performed for the G and B signals.
1-16. VIDEO OUT Amplifier
IC! 19 is used to drive the R signal cathode of the CRT.
The same is performed for the G and B signals.
1-17. G2 Control
Of the G2 R signal, G2 G signal, and G2 B signal, the sig~ al
with the lowest voltage is input to IC705 (1/2), compared with
the reference voltage (G2 REF) to become the G2 CONTROL
signal, and output from Pin (106) of CNl to the PA board
10
control the G2 voltage of the CRT.
2. ABL, Overload Detection
At IC901 (1/2), the ABL voltage and reference voltage (-1 Ytic)
are compared. Normally, the ABL voltage is above -1 Vdc and
therefore the output level of IC901 (1/2) is HIGH. If the A13L
voltage goes down and it becomes less than -1 Vdc, the CON1.
BRT will be therefore
controlled
so that this voltage ~ill
become -1 Vdc (constant). The output level of IC901 (1/2; is
set to lower than the CONTRAST voltage and therefore the
OVERLOAD
signal and therefore
the OVERLOAD
sigi al
output from IC904
(1/2)
beccomes HIGH.
3. Control Circuit
The sub CPU (IC902) performs serial communication
w:ch
system controller
using the three signals MISO, MOS!, nd
SCLK, and outputs
the control
signal according
to he
instructions of the system controller.
This IC also reads the adjustment data of the EEPROM (IC9ij~)
and outputs the adjustment voltage from the D/A convert er
(IC906 to IC91 l).
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