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Sony BVM-14E1E Operation And Maintenance Manual page 73

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3.
Protection Circuit
3-1. H.STOP, V.STOP Detection Circuit
The pulse generated for L4 l and LlOl by the H.DY drive
current is detected by D53 l, the voltage obtained is input to Pin
@
of IC501, and compared with the reference voltage (6 Vdc)
of Pin
@.
When no more pulses are input, the voltage of Pin
@
of IC501 falls below the reference voltage so that the H.STOP
signal output from Pin
(D
becomes LOW.
The pulse generated for R606 by the V .DY drive current is
amplified by IC2015 (1/2) to switch Q507. Consequently, while
pulses are input, C505 continuously discharges electricity. As a
result, the voltage of Pin
®
of IC501 does not reach the
reference voltage (6 Vdc) of Pin@ and when no more pulses
are input, the voltage of Pin
@
exceeds the reference voltage of
Pin@,
and therefore the V.STOP signal output from Pin
0
becomes LOW.
When the H.STOP or V.STOP signal becomes LOW, Q502
turns OFF, Q505 turns ON, and the HY.DRY. pulse output is
stopped. At the same time, as Q501 also turns ON, Q54 to Q56
turn ON, the E PROT signal becomes HIGH, and the power
supply circuit sets into the standby state, Q57 also turns ON,
and the +B PROT signal becomes LOW to indicate that a sub
CPU error has occurred.
3-2. Excessive Current Protection Circuit for
Horizontal Deflection Circuit Power Supply
When the current of the horizontal deflection_ circuit power
supply becor.nes abnormally great, Q52 turns ON. As a result,
Q54 to Q57 turn ON, the E PROT signal becomes HIGH, and
the +B PROT signal becomes LOW.
4.
Control Circuit
The sub CPU (1C7001) performs serial communication with the
system control CPU of the BC board using the three signals
MISO, MOSI, and SCLK, and outputs the control signals
POWER ON, DEGAUSE, AFC SW, H.DELAY, V.DELAY,
etc. according to the instructions of the system control CPU (BC
board I Cl). It also reads the adjustment data of the EEPROM
(IC7004) and output the adjustment voltage from the D/A
converter (IC7005). In addition, it also controls the waveform
output from IC! 12, ICl 15, and ICl 18 of the D board. The
following protect detection signals are transmitted to the system
control CPU from the sub CPU.
H.STOP, V.STOP,+B.PROT,HV_OVP
IK_PROT, HY _OVP, G.PROTl-4
3-19
3-4. D Board Descriptions
1-1. Signal Generator (IC105)
The deflection correction waveform is generated.
Based on the V.PULSE obtained by waveform-shaping
the
V .SAW
waveform output from IC2007 of the E board at
IC2011, the V period deflection correction signals (V 4TH,
VSIN, VPARA, and VSAW) are generated.
Based on the
AFC.PULSE waveform-shaped by IC2001 (Q25 to Q28) of the
E board, the H period deflection correction signals (HSA W,
HPARA, and HSQ) are generated.
1-2. DEFLECTION Generator
Based on the VSIN, V.PARA+, and VSAW+ signals output
from the signal generator (IC105), the following signals are
generated. The signal level and waveform can be varied using
the serial data from the system control circuit.
H. STAT. C, V. DRIVE, V. CONY T & B,
H. BAL, H. CENT, V. CONY. C, H. LIN. GAIN,
1-3. H. CONVER Generator
Based on the
VSIN, V.PARA+, V.PARA-,
and
VSAW+
signals
output from the signal generator (IC105), the following H
convergence correction signals are generated. The signal level
and waveform can be varied using the serial data from the
system control circuit.
H.CONV.C,STAT,V.STAT,H.C.L,H.C.R
1-4. D/A Converter
Based on the V4TH, V.PARA+, and VSAW+ signals output
from the signal generator (IC105), the D/A conversion reference
voltage is modulated and the following signals are generated.
The signal level can be varied using the serial data from the
system control circuit.
The adjustment voltage is also output.
• Modulated by V 4TH signal
CORNER PIN
• Modulated by VPARA+ signal
H. MID. PIN, H. CENTER. PIN,
DFY, T&B, DFY. SIDE
• Modulated by VSA W + signal.
DFY. PHASE
• Adjustment voltage
DFX.CENTER,DFX.PHASE
1-5. NTC Signal Generation
The V.CONV.T&B signal output from ICl 15 (DEFLECTION
GEN) and the V.STAT signal generated by IC112 (H.CONVER
GEN) are added and inverted by IC108 to create the NTC
signal. The adjusting points are the following three.
V.STAT
V.CONV. TOP
V.CONV. BOT
1-6. H.CONV. SIDE Signal Generation
IC108 modulates the H.C.L signal or H.C.R signal generated by
ICl 12 (H.CONVER GEN) using the H.PARA+ signal output by
IC105 (signal generator) to create the H.CONV.S signal. As for
the HSQ signal, the H.C.L signal is selected at the left side of
the screen, while the H.C.R signal is selected at the right side of
the screen.
There are 5 adjusting points on the left and right sides each.
1-7. H.LIN Signal Generation
IC203, IC108, and ICl 19 modulate and add the H.PARA-
signal and H.SAW signal output by IC105 (signal generator)
using the H.LIN GAIN signal and H.UN BAL signal output by
ICl 15 (DEFLECTION
GEN), and H.MID.PIN signal and
H.CENT.PIN signal output by ICl 18 (D/ A converter) to create
the H.LIN signal.
1-8. D.F.X. Signal, D.F.Y. Signal Generation
IC301 modulates and adds the H.SAW+ signal and H.PARA-
signal
output "by IC105
(signal
generator)
using the
DFX.PHASE signal, DFX SIDE signal, DFX CENTER voltage
output by ICl 18 (D/A converter) and V.PARA-
signal output
by IC105 to create the D.F.X signal.
ICl 11 (2/2) adds the DFY.PHASE signal and DFY.T&B signal
output by ICl 18 (D/A converter) with the V.PARA+ signal
output by IC105 (signal generator) to create the D.F. YX signal.
3-20
D Board Block Diagram
CNIOI tl/21
~----
L.MOSI
18
L.
SCLK
PA6
··~
PA4
RESET
AFC. P
15
OFX. BLK
11
D
TPI02
AFC. P

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